Intel® MAX™ 10 Embedded Memory User Guide

ID 683431
Date 9/17/2021
Public
Document Table of Contents

8. FIFO IP Core References

The FIFO IP core implements the FIFO mode, enabling you to use the memory blocks as FIFO buffers.

  • Use the FIFO IP core in single clock FIFO (SCFIFO) and dual clock FIFO (DCFIFO) modes to implement single- and dual-clock FIFO buffers in your design.
  • Dual clock FIFO buffers are useful when transferring data from one clock domain to another clock domain.
  • The M9K memory blocks do not support simultaneous read and write from an empty FIFO buffer.
Figure 24.  FIFO IP Core: SCFIFO Mode Signals
Figure 25. FIFO IP Core: DCFIFO Mode Signals

Did you find the information on this page useful?

Characters remaining:

Feedback Message