Intel® MAX™ 10 Embedded Memory User Guide

ID 683431
Date 9/17/2021
Public
Document Table of Contents

8.1. FIFO IP Core Signals for Intel® MAX® 10 Devices

Table 27.  FIFO IP Core Input Signals
Signal Required Description
clock Yes Positive-edge-triggered clock.
wrclk Yes Positive-edge-triggered clock. Synchronizes the following ports:
  • data
  • wrreq
  • wrfull
  • wrempty
  • wrusedw
rdclk Yes Positive-edge-triggered clock. Synchronizes the following ports:
  • q
  • rdreq
  • rdfull
  • rdempty
  • rdusedw
data Yes Holds the data to be written in the FIFO IP core when the wrreq signal is asserted.

If you manually instantiate the FIFO IP core, ensure that the port width is equal to the How wide should the FIFO be? parameter.

wrreq Yes Assert this signal to request for a write operation.

Ensure that the following conditions are met:

  • Do not assert the wrreq signal when the full (for the FIFO IP core in SCFIFO mode) or wrfull (for the FIFO IP core in DCFIFO mode) port is high. Enable the overflow protection circuitry or turn on the Disable overflow checking. Writing to a full FIFO will corrupt contents parameter so that the FIFO IP core can automatically disable the wrreq signal when it is full.
  • The wrreq signal must meet the functional timing requirement based on the full or wrfull signal.
  • Do not assert the wrreq signal during the deassertion of the aclr signal. Violating this requirement creates a race condition between the falling edge of the aclr signal and the rising edge of the write clock if the wrreq port is set to high.
rdreq Yes Assert this signal to request for a read operation. The rdreq signal acts differently in normal synchronous FIFO mode and show-ahead mode synchronous FIFO modes.

Ensure that the following conditions are met:

  • Do not assert the rdreq signal when the empty (for the FIFO IP core in SCFIFO mode) or rdempty (for the FIFO IP core in DCFIFO mode) port is high. Enable the underflow protection circuitry or turn on the Disable underflow checking. Reading from an empty FIFO will corrupt contents parameter so that the FIFO IP core can automatically disable the rdreq signal when it is empty.

The rdreq signal must meet the functional timing requirement based on the empty or rdempty signal.

sclr No Assert this signal to clear all the output status ports, but the effect on the q output may vary for different FIFO configurations. There are no minimum number of clock cycles for aclr signals that must remain active.
aclr No
Table 28.  FIFO IP Core Output Signals
Signal Required Description
q Yes Shows the data read from the read request operation. In SCFIFO and DCFIFO modes, the width of the q port must be equal to the width of the data port. If you manually instantiate the IPs, ensure that the port width is equal to the How wide should the FIFO be? parameter. In DCFIFO_MIXED_WIDTHS mode, the width of the q port can be different from the width of the data port. If you manually instantiate the IP, ensure that the width of the q port is equal to the Use a different output width parameter. The IP supports a wide write port with a narrow read port, and vice versa. However, the width ratio is restricted by the type of RAM block, and in general, are in the power of 2.
full No When asserted, the FIFO IP core is considered full. Do not perform write request operation when the FIFO IP core is full. In general, the rdfull signal is a delayed version of the wrfull signal. However, the rdfull signal functions as a combinational output instead of a derived version of the wrfull signal. Therefore, you must always refer to the wrfull port to ensure whether or not a valid write request operation can be performed, regardless of the target device.
wrfull
rdfull
empty No When asserted, the FIFO IP core is considered empty. Do not perform read request operation when the FIFO IP core is empty. In general, the wrempty signal is a delayed version of the rdempty signal. However, the wrempty signal functions as a combinational output instead of a derived version of the rdempty signal. Therefore, you must always refer to the rdempty port to ensure whether or not a valid read request operation can be performed, regardless of the target device.
wrempty
rdempty
almost_full No Asserted when the usedw signal is greater than or equal to the Almost full parameter. It is used as an early indication of the full signal.
almost_empty No Asserted when the usedw signal is less than the Almost empty parameter. It is used as an early indication of the empty signal.
usedw No Show the number of words stored in the FIFO. Ensure that the port width is equal to the usedw[] parameter if you manually instantiate the FIFO IP core in SCFIFO or DCFIFO modes. In DCFIFO_MIXED_WIDTH mode, the width of the wrusedw and rdusedw ports must be equal to the usedw[] and Use a different output width parameters respectively.
wrusedw
rdusedw

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