Intel® MAX™ 10 Embedded Memory User Guide

ID 683431
Date 9/17/2021
Public
Document Table of Contents

2.1.7. Address Clock Enable Support

  • The address clock enable feature holds the previous address value for as long as the address clock enable signal (addressstall) is enabled (addressstall = 1).
  • When you configure M9K memory blocks in dual-port mode, each port has its own independent address clock enable.
  • Use the address clock enable feature to improve the effectiveness of cache memory applications during a cache-miss.
  • The default value for the addressstall signal is low.
  • The address register output feeds back to its input using a multiplexer. The addressstall signal selects the multiplexer output.
Figure 3. Address Clock Enable Block Diagram

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