1. Intel® MAX® 10 Embedded Memory Overview 2. Intel® MAX® 10 Embedded Memory Architecture and Features 3. Intel® MAX® 10 Embedded Memory Design Consideration 4. RAM: 1-Port IP Core References 5. RAM: 2-PORT IP Core References 6. ROM: 1-PORT IP Core References 7. ROM: 2-PORT IP Core References 8. FIFO IP Core References 9. Shift Register (RAM-based) IP Core References 10. ALTMEMMULT IP Core References 11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide
2.1.7. Address Clock Enable Support
- The address clock enable feature holds the previous address value for as long as the address clock enable signal (addressstall) is enabled (addressstall = 1).
- When you configure M9K memory blocks in dual-port mode, each port has its own independent address clock enable.
- Use the address clock enable feature to improve the effectiveness of cache memory applications during a cache-miss.
- The default value for the addressstall signal is low.
- The address register output feeds back to its input using a multiplexer. The addressstall signal selects the multiplexer output.
Figure 3. Address Clock Enable Block Diagram