1. Intel® MAX® 10 Embedded Memory Overview 2. Intel® MAX® 10 Embedded Memory Architecture and Features 3. Intel® MAX® 10 Embedded Memory Design Consideration 4. RAM: 1-Port IP Core References 5. RAM: 2-PORT IP Core References 6. ROM: 1-PORT IP Core References 7. ROM: 2-PORT IP Core References 8. FIFO IP Core References 9. Shift Register (RAM-based) IP Core References 10. ALTMEMMULT IP Core References 11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide
2.1.8. Asynchronous Clear
You can selectively enable asynchronous clear per logical memory using the RAM: 1-PORT and RAM: 2-PORT IP cores.
Support of asynchronous clear in the M9k memory block:
- Read address registers—input registers other than read address registers are not supported. Asserting asynchronous clear to the read address register during a read operation might corrupt the memory content.
- Output registers—if applied to output registers, the asynchronous clear signal clears the output registers and the effects are immediate. If your RAM does not use output registers, you can still clear the RAM outputs using the output latch asynchronous clear feature.
- Output latches
Figure 6. Output Latch Asynchronous Clear Waveform
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