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1. Intel® MAX® 10 Embedded Memory Overview
2. Intel® MAX® 10 Embedded Memory Architecture and Features
3. Intel® MAX® 10 Embedded Memory Design Consideration
4. RAM: 1-Port IP Core References
5. RAM: 2-PORT IP Core References
6. ROM: 1-PORT IP Core References
7. ROM: 2-PORT IP Core References
8. FIFO IP Core References
9. Shift Register (RAM-based) IP Core References
10. ALTMEMMULT IP Core References
11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide
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9.2. Shift Register (RAM-based) IP Core Parameters for Intel® MAX® 10 Devices
Option | Values | Description | ||
---|---|---|---|---|
How wide should the "shiftin" input and the "shiftout" output buses be? | 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, and 256. | Specifies the width of the input pattern. | ||
How many taps would you like? | 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 24, 32, 48, 64, 96, and 128. | Specifies the number of regularly spaced taps along the shift register. | ||
Create groups for each tap output | On/Off | Creates groups for each tap output. | ||
How wide should the distance between taps be? | 3, 4, 5, 6, 7, 8, 16, 32, 64, and 128 | Specifies the distance between the regularly spaced taps in clock cycles. This number translates to the number of RAM words that will be used. The value must be at least 3. | ||
Create a clock enable port | On/Off | Creates the clken port | ||
Create an asynchronous clear port | On/Off | Creates the aclr port. | ||
What should the RAM block type be? | Auto, M9K | Specifies the RAM block type. |
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