Intel® MAX™ 10 Embedded Memory User Guide

ID 683431
Date 9/17/2021
Public
Document Table of Contents

9.2. Shift Register (RAM-based) IP Core Parameters for Intel® MAX® 10 Devices

Table 32.   Shift Register (RAM-based) IP Core Parameters for Intel® MAX® 10 Devices This table lists the IP core parameters applicable to Intel® MAX® 10 devices.
Option Values Description
How wide should the "shiftin" input and the "shiftout" output buses be? 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, and 256. Specifies the width of the input pattern.
How many taps would you like? 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 24, 32, 48, 64, 96, and 128. Specifies the number of regularly spaced taps along the shift register.
Create groups for each tap output On/Off Creates groups for each tap output.
How wide should the distance between taps be? 3, 4, 5, 6, 7, 8, 16, 32, 64, and 128 Specifies the distance between the regularly spaced taps in clock cycles. This number translates to the number of RAM words that will be used. The value must be at least 3.
Create a clock enable port On/Off Creates the clken port
Create an asynchronous clear port On/Off Creates the aclr port.
What should the RAM block type be? Auto, M9K Specifies the RAM block type.

Did you find the information on this page useful?

Characters remaining:

Feedback Message