Intel® MAX™ 10 Embedded Memory User Guide

ID 683431
Date 9/17/2021
Public
Document Table of Contents

2.1.5. Byte Enable

  • Memory block that are implemented as RAMs support byte enables.
  • The byte enable controls mask the input data, so that only specific bytes of data are written. The unwritten bytes retain the values written previously.
  • The write enable (wren) signal, together with the byte enable (byteena) signal, control the write operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren signal controls the writing.
  • The byte enable registers do not have a clear port.
  • M9K blocks support byte enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits.
  • Byte enables operate in a one-hot fashion. The Least Significant Bit (LSB) of the byteena signal corresponds to the LSB of the data bus. For example, if byteena = 01 and you are using a RAM block in ×18 mode, data[8:0] is enabled and data[17:9] is disabled. Similarly, if byteena = 11, both data[8:0] and data[17:9] are enabled.
  • Byte enables are active high.

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