| data |
Yes |
Data input to the memory. The data port is required and the width must be equal to the width of the q port. |
| address |
Yes |
Address input to the memory. |
| wren |
Yes |
Write enable input for the wraddress port. |
| addressstall_a |
Optional |
Address clock enable input to hold the previous address of address_a port for as long as the addressstall_a port is high. |
| clock |
Yes |
The following list describes which of your memory clock must be connected to the clock port, and port synchronization in different clocking modes:
- Single clock—Connect your single source clock to clock port. All registered ports are synchronized by the same source clock.
- Read/Write—Connect your write clock to clock port. All registered ports related to write operation, such as data_a port, address_a port, wren_a port, and byteena_a port are synchronized by the write clock.
- Input/Output—Connect your input clock to clock port. All registered input ports are synchronized by the input clock.
- Independent clock—Connect your port A clock to clock port. All registered input and output ports of port A are synchronized by the port A clock.
|
| clkena |
Optional |
Clock enable input for clock port. |
| rden |
Optional |
Read enable input for rdaddress port. |
| aclr |
Optional |
Asynchronously clear the registered input and output ports. The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as indata_aclr, wraddress_aclr, and so on. |
| inclock |
Optional |
The following list describes which of your memory clock must be connected to the inclock port, and port synchronization in different clock modes:
- Single clock—Connect your single source clock to inclock port and outclock port. All registered ports are synchronized by the same source clock.
- Read/Write—Connect your write clock to inclock port. All registered ports related to write operation, such as data port, wraddress port, wren port, and byteena port are synchronized by the write clock.
- Input/Output—Connect your input clock to inclock port. All registered input ports are synchronized by the input clock.
|
| inclocken |
Optional |
Clock enable input for inclock port. |
| outclock |
Optional |
The following list describes which of your memory clock must be connected to the outclock port, and port synchronization in different clock modes:
- Single clock—Connect your single source clock to inclock port and outclock port. All registered ports are synchronized by the same source clock.
- Read/Write—Connect your read clock to outclock port. All registered ports related to read operation, such as rdaddress port, rdren port, and q port are synchronized by the read clock.
- Input/Output—Connect your output clock to outclock port. The registered q port is synchronized by the output clock.
|
| outclocken |
Optional |
Clock enable input for outclock port. |