AN 739: Altera 1588 System Solution

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ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.4.4.2. Transceiver Registers

For the description of each PHY register, refer to the Altera Transceiver PHY IP Core User Guide. The address offset in the following tables is in byte addressing, while the register map table in the Altera Transceiver PHY IP Core User Guide is in word addressing.

Note: Altera recommends maintain the register settings for this module as set in the reference design for optimum operation.
Table 8.  PMA Registers
Byte Offset Bit R/W Name
0x0088 RO pma_tx_pll_is_locked
0x0110 1 RW reset_tx_digital
2 RW reset_rx_analog
3 RW reset_rx_digital
0x0184 RW phy_serial_loopback
0x0190 RW pma_rx_set_locktodata
0x0194 RW pma_rx_set_locktoref
0x0198 RO pma_rx_is_lockedtodata
0x019C RO pma_rx_is_lockedtoref
0x02A0 0 RW tx_invpolarity
1 RW rx_invpolarity
2 RW rx_bitreversal_enable
3 RW rx_bytereversal_enable
4 RW force_electrical_idle
0x02A4 0 R rx_syncstatus
1 R rx_patterndetect
2 R rx_rlv
3 R rx_rmfifodatainserted
4 R rx_rmfifodatadeleted
5 R rx_disperr
6 R rx_errdetect
Table 9.  PCS Registers
Byte Offset Bit R/W Name
0x0200   RW Indirect_addr
0x0204 2 RW RCLR_ERRBLK_CNT
3 RW RCLR_BER_COUNT
0x0208 1 RO HI_BER
2 RO BLOCK_LOCK
3 RO TX_FULL
4 RO RX_FULL
5 RO RX_SYNC_HEAD_ERROR
6 RO RX_SCRAMBLER_ERROR
7 RO Rx_DATA_READY
Level Two Title