AN 739: Altera 1588 System Solution

ID 683410
Date 1/28/2016
Public
Document Table of Contents

1.4.4.2. Transceiver Registers

For the description of each PHY register, refer to the Altera Transceiver PHY IP Core User Guide. The address offset in the following tables is in byte addressing, while the register map table in the Altera Transceiver PHY IP Core User Guide is in word addressing.

Note: Altera recommends maintain the register settings for this module as set in the reference design for optimum operation.
Table 8.  PMA Registers
Byte Offset Bit R/W Name
0x0088 RO pma_tx_pll_is_locked
0x0110 1 RW reset_tx_digital
2 RW reset_rx_analog
3 RW reset_rx_digital
0x0184 RW phy_serial_loopback
0x0190 RW pma_rx_set_locktodata
0x0194 RW pma_rx_set_locktoref
0x0198 RO pma_rx_is_lockedtodata
0x019C RO pma_rx_is_lockedtoref
0x02A0 0 RW tx_invpolarity
1 RW rx_invpolarity
2 RW rx_bitreversal_enable
3 RW rx_bytereversal_enable
4 RW force_electrical_idle
0x02A4 0 R rx_syncstatus
1 R rx_patterndetect
2 R rx_rlv
3 R rx_rmfifodatainserted
4 R rx_rmfifodatadeleted
5 R rx_disperr
6 R rx_errdetect
Table 9.  PCS Registers
Byte Offset Bit R/W Name
0x0200   RW Indirect_addr
0x0204 2 RW RCLR_ERRBLK_CNT
3 RW RCLR_BER_COUNT
0x0208 1 RO HI_BER
2 RO BLOCK_LOCK
3 RO TX_FULL
4 RO RX_FULL
5 RO RX_SYNC_HEAD_ERROR
6 RO RX_SCRAMBLER_ERROR
7 RO Rx_DATA_READY