AN 739: Altera 1588 System Solution

ID 683410
Date 1/28/2016
Public
Document Table of Contents

1.4.3. System Parameters

This section describes the parameters used for the modules used in the reference design that are instantiated from the Quartus II software IP catalog.
The following table shows the parameter settings in the Altera 10G-bps Ethernet MAC IP for this reference design. Altera recommends keeping the specified parameter settings as set in the project when using the reference design.
Table 1.  Parameters Settings for Altera 10G-bps Ethernet MAC IP
Parameter Setting
Speed 10 Gbps
Datapath option: TX & RX
Enable preamble pass-through mode Turn off
Enable priority-based flow control (PFC) Turn off
Enable supplementary address Turn off
Enable CRC on transmit path Turn on
Enable statistics collection Turn on
Statistics counters: Memory-based
Enable time stamping Turn on
Enable PTP one-step clock support Turn on
The following table shows the parameter settings in the Altera 10GBASE-R PHY IP for this reference design. Altera recommends keeping the specified parameter settings as set in the project when using the reference design.
Table 2.  Parameters Settings for Altera 10GBASE-R PHY IP
Parameter Setting
Number of channels: 1
Mode of operation: duplex
PLL type: CMU
Reference clock frequency: 644.53125 MHz
Enable additional control and status pins Turn off
Enable rx_recovered_clk_pin Turn off
Enable pll_locked_status port Turn off
Enable rx_coreclkin_port Turn off
Enable embedded reset controller Turn on
Enable IEEE 1588 latency adjustment ports Turn on
The following table shows the parameter settings in the Altera Transceiver Reconfiguration Controller IP for this reference design. Altera recommends keeping the specified parameter settings as set in the project when using the reference design.
Table 3.  Parameters Settings for Altera Transceiver Reconfiguration Controller IP
Parameter Setting
Number of reconfiguration interfaces: 2
Optional interface grouping: Leave blank
Enable offset cancellation Turn on by default
Enable duty cycle calibration Turn off
Create optional calibration status ports Turn off
Enable Analog controls Turn on
Enable channel/PLL reconfiguration Turn off
Enable PLL reconfiguration support block Turn off
The following table shows the parameter settings in the Altera Ethernet IEEE 1588 Time of Day Clock IP for this reference design. Altera recommend keeping the specified parameter settings as set in the project when using the reference design.
Table 4.  Parameters Settings for Altera Ethernet IEEE 1588 Time of Day Clock IP
Parameter Setting
DEFAULT_NSEC_PERIOD: 6
DEFAULT_FNSEC_PERIOD: 0x00006666
DEFAULT_NSEC_ADJPERIOD: 6
DEFAULT_FNSEC_ADJPERIOD: 0x00006666