AN 739: Altera 1588 System Solution

ID 683410
Date 1/28/2016
Document Table of Contents

1.4.4. System Register Map

This section list the base address, the register offset and register descriptions for each modules in the reference design.

The following table shows the base address map for each block in the Altera 1588 reference design.

Table 5.  Reference Design Block Register Map
Base address Block
0xFF20_0140 Altera ToD Clock
Channel 0
0xFF21_0000 Altera 10G-bps Ethernet MAC
0xFF21_8000 Altera 10G BASE-R PHY
0xFF21_8800 PTP Control
0xFF21_8C00 Altera Reconfiguration Bundle
Channel 1
0xFF22_0000 Altera 10G-bps Ethernet MAC
0xFF22_8000 Altera 10G BASE-R PHY
0xFF22_8800 PTP Control
0xFF22_8C00 Altera Reconfiguration Bundle