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1.2.1. Understanding the Different PTP Clocks
1.2.2. Precision Time Protocol (PTP) Synchronization Process
1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System
1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System
1.2.5. Functional Flow for A 1588 Boundary Clock Mode System
1.2.6. Timestamp Packet Functional Flow in Linux Driver
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1.4.4. System Register Map
This section list the base address, the register offset and register descriptions for each modules in the reference design.
The following table shows the base address map for each block in the Altera 1588 reference design.
Base address | Block |
---|---|
0xFF20_0140 | Altera ToD Clock |
Channel 0 | |
0xFF21_0000 | Altera 10G-bps Ethernet MAC |
0xFF21_8000 | Altera 10G BASE-R PHY |
0xFF21_8800 | PTP Control |
0xFF21_8C00 | Altera Reconfiguration Bundle |
Channel 1 | |
0xFF22_0000 | Altera 10G-bps Ethernet MAC |
0xFF22_8000 | Altera 10G BASE-R PHY |
0xFF22_8800 | PTP Control |
0xFF22_8C00 | Altera Reconfiguration Bundle |