AN 739: Altera 1588 System Solution

ID 683410
Date 1/28/2016
Document Table of Contents MAC Registers

For the description of each MAC register, refer to the 10-Gbps Ethernet MAC Megacore Function User Guide. The address offset in the following tables is in byte, while the register map table in the 10-Gbps Ethernet MAC Megacore Function User Guide is in word.

Note: Altera recommends maintain the register settings for this module as set in the reference design for optimum operation.
Table 6.  MAC Register Components and Offset Range
Component Byte Offset Range
RX Packet Transfer 0x0000:0x00FF
RX Pad/CRC Remover 0x0100:0x01FF
RX CRC Checker 0x0200:0x02FF
RX Packet Overflow 0x0300:0x03FF
RX Preamble Control 0x0400:0x04FF
RX Lane Decoder 0x0500:0x1FFF
RX Frame Decoder 0x2000:0x2FFF
RX Statistics Counters 0x3000:0x3FFF
TX Packet Transfer 0x4000:0x40FF
TX Pad Inserter 0x4100:0x41FF
TX CRC Inserter 0x4200:0x42FF
TX Packet Underflow 0x4300:0x43FF
TX Preamble Control 0x4400:0x44FF
TX Pause Frame Control and Generator 0x4500:0x45FF
TX PFC Generator 0x4600:0x47FF
TX Address Inserter 0x4800:0x5FFF
TX Frame Decoder 0x6000:0x6FFF
TX Statistics Counters 0x7000:0x7FFF
Table 7.  MAC Registers for IEEE 1588v2 Feature
Register Byte Offset
rx_period 0x0440
rx_adjust_fns 0x0448
rx_adjust_ns 0x044C
tx_period 0x4440
tx_adjust_fns 0x4448
tx_adjust_ns 0x444C