AN 739: Altera 1588 System Solution

ID 683410
Date 1/28/2016
Public
Document Table of Contents

1.4.5.3. HPS Signals

Table 14.  Arria V HPS Interface Signals
Signal Direction Width Description
HPS DDR3 SDRAM
hps_memory_mem_a
Output 15 Address bus.
hps_memory_mem_ba
Output 3 Bank address.
hps_memory_mem_ck
mem_ck_n
Output 1 Memory clock.
mem_cke
Output 1

Clock enable.

mem_cs_n
Output 1

Chip select..

mem_ras_n
Output 1

Row address strobe.

mem_cas_n
Output 1

Column address strobe.

mem_we_n
Output 1

Write enable.

mem_reset_n
Output 1

Reset

mem_dq
Bidirectional 40

Data.

mem_dqs 
Bidirectional 5

Data strobe.

mem_dqs_n
Bidirectional 5

Data strobe.

mem_odt
Output 1

On-die termination.

mem_dm
Output 5

Data mask.

oct_rzqin Input 1 OCT reference resistor pins for RZQ.
HPS Peripheral
hps_uart0_TX
Output 1 Output signal for UART channel 0.

This signal is required for serial console communication to host.

hps_uart0_RX
Input 1 Input signal for UART channel 0.

This signal is required for serial console communication to host.