1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.4.2. Clocking and Reset Scheme
The following figure shows the clocking scheme implemented in the reference design. The clock crossing logic between Arria V SoC and 10Gbps Ethernet MAC clock is handled by Qsys. Refer to Clock and Reset Signals for information related to the clock signals available in the reference design.
Figure 22. Reference Design Clocking Scheme
This reference implements the Altera Transceiver PHY Reset Controller IP to handle the Ethernet system reset sequence.
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