AN 739: Altera 1588 System Solution

ID 683410
Date 1/28/2016
Document Table of Contents

1.4.2. Clocking and Reset Scheme

The following figure shows the clocking scheme implemented in the reference design. The clock crossing logic between Arria V SoC and 10Gbps Ethernet MAC clock is handled by Qsys. Refer to Clock and Reset Signals for information related to the clock signals available in the reference design.
Figure 22. Reference Design Clocking Scheme

This reference implements the Altera Transceiver PHY Reset Controller IP to handle the Ethernet system reset sequence.