AN 739: Altera 1588 System Solution

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ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1. Altera 1588 System Solution

This Application Note describes the overview concept of IEEE 1588v2 standard and Precision Time Protocol as well as the procedure and architecture of Altera 1588 system solution reference design using Altera Arria V SoC, 10G Ethernet MAC with 10G BASE-R PHY hardware IP and software stack which is build based on Linux kernel v3.16, consists of PTP stack LinuxPTP v1.5, a preloader, 10G-bps Ethernet MAC driver and a PTP driver.

The objectives of the reference design include the following:
  • 6.99ns timestamp accuracy using Altera 1588 hardware IP and Linux PTP software stack for 10Gbps speed.
  • Offset adjustment capability from the system perspective for an ordinary clock (OC) in slave mode.
  • Altera 1588 IP usability from the Linux system perspective for an ordinary clock in master mode.
This reference design includes hardware system design and software stack which allow you to:
  • Perceive the usability of the hardware IP from various perspectives of the system solution.
  • Assess the accuracy requirements in relation to the capability of this reference design.
  • Replace the existing Linux PTP application with other PTP applications.

Section Content
Altera 1588 System Level Overview
Precision Time Protocol (PTP) Concept in A 1588 System
Reference Design Walk-through
System Architecture
Altera 1588 System Solution Document Revision History

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