AN 739: Altera 1588 System Solution

ID 683410
Date 1/28/2016
Document Table of Contents

1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System

The following figure illustrates timestamp synchronization flow using 1-step mechanism transparent clock mode on the Altera 1588 system. In this figure, the transparent clock consists of two Altera 1588 IP cores to create two ports system; one port as PTP packet input port and another as PTP packet output port. The residence delay is calculated from the timestamp of the input port to the timestamp of the output port.

Figure 6. Functional Flow For 1588 Transparent Clock Mode with Multiple ToD
  1. PTP packet enters the FPGA through cable A and the Mac RX 1588 logic generates timestamp Ti1.
  2. The packet parser validates the PTP packet before sending it to the user logic along with the timestamp information, ignoring all timestamps for non-PTP packets.
  3. The user logic at the egress port send the PTP packet along with timestamp Ti1 to the packet parser of the egress port.
  4. The packet parser, then validates the PTP packet and send the packet along with the timestamp Ti1 to Mac Tx 1588 logic along with the required command.
  5. Mac Tx 1588 logic generates timestamp Te1 and updates the correction factor (CF) in the packet header. The CF field contains the new residence delay, calculated as CF' = CF + Te1-Ti1.
  6. The PHY, then transmits the PTP packet to the network.
  7. The same flow from step 1 to step 6 applies to the PTP packet received by cable B, with the timestamp components of Ti2 and Te2.

For 2-step mechanism, the CPU collects the ingress and egress timestamps from FIFOs, but the PTP packet remain unchanged. The ingress port receives a follow-up packet from the network and Mac Rx 1588 logic generates a timestamp for the follow-up packet. The packet parser verifies it is a follow-up packet and send it to the CPU via user logic. The CPU updates the follow-up packet after matching the packet's fingerprints with the new correction field of CF'=CF + Te - Ti before sending it to the egress port.

The ingress and egress port of a TC mode system may have a single or multiple ToD modules. For system with single ToD module, the ToD operates using the transmit clock to use a single clock to calculate the residence delay. For system with multiple ToD modules, a ToD synch module is used to synchronize the residence delay between the ToD modules.
Figure 7. Functional Flow For 1588 Transparent Clock Mode with Single ToD