1.2.2. Precision Time Protocol (PTP) Synchronization Process
The synchronization process involves ToD (Time of Day) offset correction and frequency correction between a master clock and a slave clock. The slave clock collects necessary data to synchronize its clock with master’s clock through event messages. Below is the synchronization process flow:
- The slave collects the timestamps of T1, T2, T3 and T4 through the event messages; Sync, Delay_Req, and Delay_Resp and calculates the mean path delay (MPD).
- At the next sync message, the slave calculates the ToD offset by subtracting the MPD from the result of T6-T5 and adjusts its ToD counter accordingly.
- Next, the slave clock calculates the frequency offset by comparing the time difference in frequency between 2 successively transmitted and received sync messages per the following equation:
Frequency offset = (Fo - Fr)/Fr
where Fo = 1/(T5-T1) and Fr = 1/(T6-T2),
T1 = Initial time for first transmitted sync message from master clock
T2 = Initial time for first received sync message from slave clock
T5 = Initial time for second transmitted sync message from master clock
T6 = Initial time for second received sync message from slave clock
- The slave clock calculates ToD offset and frequency offset continuously to maintain its ToD counter corresponding to the master clock to the best possible accuracy. This is most often accomplished through frequent syntonization offset adjustments after the initial ToD offset adjustment and occasional ToD offset adjustments.
The function of TC nodes is to calculate the residence delays of the PTP packets between a master clock and a slave clock to provide a more accurate offset. However, a long chain of TC nodes increases inaccuracy in synchronization.
The BC device is used to break the long chain of TC nodes and maintain the accuracy of the synchronization. The BC device has a slave clock port synchronizing to a master clock external to the BC system. The master ports in a BC system use the timescale maintained by the slave clock within the same BC system.
Altera Ethernet MAC and transceiver IPs with fractional arithmetic capability can provide highest accuracy of 6.99ns for Ethernet link of 10Gbps speed, facilitating synchronization required even for stringent applications such as telecom and mobile backhaul. Further, the design facilitates visual demonstration of the achieved synchronization through PPS (pulse per second) output. The efficacy of the synchronization between the master and slave clock can be observe through the PPS output in an oscilloscope.
Did you find the information on this page useful?