AN 739: Altera 1588 System Solution

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ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.2.6. Timestamp Packet Functional Flow in Linux Driver

This section describes the timestamp packet flow between Linux driver and the system hardware.

The reference design uses TX Ingress Timestamp FIFO and RX Ingress Timestamp FIFO to store the timestamp with fingerprint. The Linux PTP driver will access these FIFO to obtain the timestamp information for PTP software processing. A FIFO status read can be omitted if the FIFO read delay is determined. CPU can read the RX FIFO without any delay while for TX FIFO, a delay is necessary and most often depends on the sum of MTU delay of a scheduled packet, DMA delays and the PTP packet transmit delays. In general, 3*MTU delay is the common value for TX FIFO read delay.

The following figure shows the timestamp packet flow between Linux driver and the system hardware for receive path.
Figure 9. Timestamp Flow Between Linux Driver and System Hardware for Receive Path
The following figure shows the timestamp packet flow between Linux driver and the system hardware for transmit path.
Figure 10. Timestamp Flow Between Linux Driver and System Hardware for Transmit Path
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