AN 739: Altera 1588 System Solution

ID 683410
Date 1/28/2016
Document Table of Contents Replacing RBF File

At times, you may need to modify the reference design according to your system requirements and recompile the reference design. You are required to regenerate the altera_eth_10g_1588_ref_design_msgdma_top.qsys file for compilation. Following are the steps to guide you in regenerating the design files and replacing the RBF file into the system image. You are required to use Quartus II Subscription Edition v14.1 for these procedures.

  1. Download the file to your computer and unzip the folder.
  2. Launch Quartus II software. In Quartus II software, click File -> Open Project and browse to av_1588_top.qpf file to open the reference design project.
  3. Once the the project file is open, click on Tools -> Qsys in the Quartus II software.
  4. In the Qsys interface, click File -> Open and browse to altera_eth_10g_1588_ref_design_msgdma_top.qsys file to open the reference design Qsys file.
  5. Once the reference design Qsys file is opened, click Generate HDL.
    Figure 19. Generating HDL File in Qsys
  6. You will see the Generation dialog box appear. You may choose Verilog or VHDL for synthesis file type.
  7. Browse to the location where you want to store the generated output files under the Output Directory and click Generate. Click Close once the files generation completed.
    Figure 20. Generation Dialog Box
  8. In Quartus II software, click Processing -> Start Compilation to recompile the reference design. You will see av_1588_top.sof file in the output_files folder once compilation is completed.
  9. Create a new text file titled option.txt with the following content.
  10. At the command prompt in Linux or DOS, type quartus_cpf -o <project_dir>/option.txt -c av_1588_top.sof soc_system.rbf to generate the .rbf (file name tag) file.
  11. You can replace the soc_system.rbf file in the SD card with the newly generated RBF file.

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