Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

32.4. TMO IP Registers

The TMO IP allows run-time configuration parameters via AXI4-Lite CPU register interface.

The IP offers the following categories of run-time configuration parameters:

  • Flow control parameters that allow you to put the TMO IP into either reset, bypass, or operational mode.
  • Status and debug parameters that provide information about compile-time parameters and current status of the TMO IP
  • Video configuration parameters that allow you to configure the input video frame geometry
  • Image statistics collection parameters that allow you to configure the tile’s dimension
Table 538.  Register Map
Register Name Byte Address Offset Access Type
vid_pid 0x000

RO

version_number 0x004

RO

reserved_area 0x140 – 0x147 Reserved
ip_information_0 0x148

RO

ip_information_1 0x14C

RO

ip_information_2 0x150

RO

vid_flow_control 0x154

RW

actv_vid_size 0x158

RW

volume_control 0x15C

RW

tmo_derived_parameters 0x160 – 0x1D0 Reserved.
roi_horizontal_pos 0x1D4 RW
roi_vertical_pos 0x1D8 RW
reserved_area 0x1D0 – 0x17F Reserved.
Table 539.   vid_pid
Bits Description

31:0

Product Identification Number.
Table 540.   version_number
Bits Description

31:0

Version Number.
Table 541.   reserved_area
Bits Description

31:0

Reserved register area
Table 542.   ip_information_0
Bits Description

27:24

Number of tiles (C_TILE)

23:16

AXI4-Stream data width

11:8

Pixels in parallel (C_PIXELS)

7:4

Components per sample (C_STREAMS)

3:0 Bits per component (C_DEPTH)
Table 543.   ip_information_1
Bits Description

29:25

Fractional precision for luminance weights (C_FRAC_PREC_MLUT)

24:20

Fractional precision for TMO volume control (C_FRAC_PREC_VOLCNTR)

19:15 Fractional precision for RGB to luma conversion (C_FRAC_PREC_RGB2LUMA)

14:10

Fractional precision for luma to RGB conversion (C_FRAC_PREC_LUMA2RGB)
9:5

Histogram address data width (C_HIST_ADDR_WIDTH)

4:0

Histogram data width (C_HIST_DATA_WIDTH)

Table 544.   ip_information_2
Bits Description

21:17

Fractional precision for interpolation (C_FRAC_PREC_INTP)

16:12

Fractional precision for histogram equalization (C_FRAC_PREC_HEQ)
11:0

Fractional precision for histogram normalization factor (C_NORM_FACT)

Table 545.   vid_flow_control
Bits Description
31

Soft-reset bit. When set to 1 the TMO IP is in reset.

2

Swap region bit for region of interest mode.

0: Process inside of the selected region and bypass outside.

1: Process outside of the selected region and process outside.

The IP ignores this bit in bypass mode.

1

Region of Interest bit. Set to 1 to put the TMO IP in region of interest mode. Swap region bit determines whether inside or outside of the region of interest is processed or bypassed.

The IP ignores this bit in bypass mode.

0 Bypass bit. Set to 1 to put the TMO IP into bypass mode.
Table 546.   actv_vid_size
Bits Description

29:16

Total number of active pixels per video line (C_WIDTH)

13:0

Total number of active lines per video frame (C_HEIGHT)

Table 547.   roi_horizontal_pos
Bits Description
29:16 Horizontal pixel coordinate where rectangular region of interest starts.
13:0 Horizontal pixel coordinate where rectangular region of interest ends.
Table 548.   roi_vertical_pos
Bits Description
29:16 Vertical pixel coordinate where rectangular region of interest starts.
13:0 Vertical pixel coordinate where rectangular region of interest ends.
Table 549.   volume_control
Bits Description

22:16

Fine-level TMO volume control. Valid range [0:100] decimal

13:0

Coarse-level TMO strength threshold. Valid range [0:9000] decimal
Table 550.   tmo_derived_parameters
Bits Description

31:0

This area is reserved for all derived parameter registers. Do not write or read from it.

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