Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)

The IP drives the Genlock controller DAC PWM output pin to high impedance if you do not drive it. Therefore, the external Genlock controller floats to either high or low, which pushes the VCXO to one of its limits. However, this floating isn’t always stable especially because of changes in temperature. Intel recommends you always drive the Genlock controller DAC PWM output pin with a known value. At this stage you can drive that pin and no contention exists on the PCB.

If the Genlock controller is free running, at some point you may need to lock to a reference clock. As you don’t know the reference clock frequency, lock from the VCXO mid value.

  1. Enable DAC driver from High Z to mid value:
    • Write DAC control register = 0x1
  2. If the IP is already locked to reference clock, return the DAC to its mid value. Leave both the PFD and LPF as they have no impact on the DAC output.