Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

17.1. About the Deinterlacer IP

The IP takes a stream of interlaced video fields and outputs progressive frames generated using a bob algorithm.

The IP passes progressive video frames through unchanged. The bob algorithm duplicates each line of a video such that the IP produces two lines of data for each one line of incoming data. The deinterlacing algorithm can be setup for:

  • Deinterlacing F0 fields while dropping F1 fields
  • Deinterlacing F1 fields while dropping F0 fields
  • Deinterlacing both F0 and F1 fields

For a regular input sequence of alternating field types, the frame rate on the output matches the input field rate when deinterlacing both F0 and F1 fields, otherwise the IP halves the field rate. The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. For full variants, the deinterlacer IP decodes input resolutions and field type by reading image information packets. Lite variants use the register interface to determine input resolutions and whether the video is progressive or interlaced. Lite variants then decode the axi4s_vid_in_tuser[1] signal to determine the incoming field's interlaced type. If you require weave or motion adaptive deinterlacing, use protocol converters and the video and image processing suite deinterlacer II IP.