Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

22.1. About the Genlock Controller IP

The Genlock Controller IP is a control loop system that matches the frequency of the voltage-controlled crystal oscillator (VCXO) clock to the selected reference clock.

You can use the IP in an FPGA to support external voltage-controlled crystal oscillator (VCXO) clock tracking to a reference clock. The IP is highly parameterizable and programmable for various scenarios.

Typically, you generate video receiver and transmitter pixel clocks and video processing clock from three different clock generators. Hence, they are asynchronous. If the video receiver and transmitter clocks are asynchronous, the output video stream drifts over time relative to the input video stream.

The Genlock Controller IP allows locking receiver and transmitter pixel clocks, to avoid any drifting or rolling effect on the output video stream. The video drifting is visually noticeable when the processing video pipeline does not include a frame buffer in it.

Figure 55. Video Processing Pipeline

The figure shows a video processing pipeline without frame buffer. It shows how adding a genlock to the input and output video affects the output video.