Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 12/12/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Key Intel® FPGA IP x
10.1. About the Chroma Key IP 10.2. Chroma Key IP Parameters 10.3. Chroma Key IP Interfaces 10.4. Chroma Key Replacement 10.5. Chroma Key IP Registers 10.6. Chroma Key IP Software API
10.1. About the Chroma Key IP x
10.1.1. Chroma Key IP Performance and Resources
11. Chroma Resampler Intel® FPGA IP x
11.1. About the Chroma Resampler IP 11.2. Chroma Resampler IP Parameters 11.3. Chroma Resampler IP Functional Description 11.4. Chroma Resampler IP Registers 11.5. Chroma Resampler IP Software API
11.1. About the Chroma Resampler IP x
11.1.1. Chroma Resampler Performance and Resources
11.3. Chroma Resampler IP Functional Description x
11.3.1. Chroma Resampler IP Interfaces
12. Clipper Intel® FPGA IP x
12.1. About the Clipper IP 12.2. Clipper IP Parameters 12.3. Clipper IP Interfaces 12.4. Clipper IP Registers 12.5. Clipper IP Software API
12.1. About the Clipper IP x
12.1.1. Clipper IP Performance and Resources
13. Clocked Video Input Intel® FPGA IP x
13.1. About the Clocked Video Input IP 13.2. Initializing the Clocked Video Input IP 13.3. Clocked Video Input IP Parameters 13.4. Clocked Video Input IP Interfaces 13.5. Clocked Video Input IP Registers 13.6. Clocked Video Input IP Software API
13.1. About the Clocked Video Input IP x
13.1.1. Clocked Video Input IP Features 13.1.2. Clocked Video Input IP Performance and Resources
14. Clocked Video to Full-Raster Converter Intel® FPGA IP x
14.1. About the Clocked Video to Full-Raster Converter IP 14.2. Clocked Video to Full-Raster Converter Parameters 14.3. Clocked Video to Full-Raster Converter Block Description 14.4. Clocked Video Converter to Full-Raster IP Registers
14.1. About the Clocked Video to Full-Raster Converter IP x
14.1.1. Clocked Video to Full-Raster Converter Features 14.1.2. Clocked Video to Full-Raster Converter Performance and Resources
14.3. Clocked Video to Full-Raster Converter Block Description x
14.3.1. Clocked Video to Full-Raster Converter Interfaces
15. Clocked Video Output Intel® FPGA IP x
15.1. About the Clocked Video Output IP 15.2. Clocked Video Output IP Parameters 15.3. Clocked Video Output IP Functional Description 15.4. Clocked Video Output IP Interfaces 15.5. Clocked Video Output IP Registers 15.6. Clocked Video Output IP Software API
15.1. About the Clocked Video Output IP x
15.1.1. Clocked Video Output IP Performance and Resources 15.1.2. Clocked Video Output IP Features
16. Color Space Converter Intel® FPGA IP x
16.1. About the Color Space Converter IP 16.2. Color Space Converter IP Parameters 16.3. Color Space Converter IP Functional Description 16.4. Color Space Converter IP Registers 16.5. Color Space Converter IP Software API
16.1. About the Color Space Converter IP x
16.1.1. Color Space Converter IP Features 16.1.2. Color Space Converter IP Performance and Resources
16.3. Color Space Converter IP Functional Description x
16.3.1. Color Space Converter IP Interfaces
17. Deinterlacer Intel® FPGA IP x
17.1. About the Deinterlacer IP 17.2. Deinterlacer Parameters 17.3. Deinterlacer Interfaces 17.4. Deinterlacer Registers 17.5. Deinterlacer IP Software API
17.1. About the Deinterlacer IP x
17.1.1. Deinterlacer Performance and Resources
18. FIR Filter Intel® FPGA IP x
18.1. About the FIR Filter 18.2. FIR Filter Parameters 18.3. FIR Filter IP Operation 18.4. FIR Filter Interfaces 18.5. FIR Filter Registers 18.6. FIR Filter IP Software API
18.1. About the FIR Filter x
18.1.1. FIR Filter IP Performance and Resources
18.3. FIR Filter IP Operation x
18.3.1. FIR Filter Processing 18.3.2. FIR Filter Precision 18.3.3. FIR Coefficient Specification 18.3.4. FIR Filter Symmetry 18.3.5. Result to Output Data Type Conversion
18.3.4. FIR Filter Symmetry x
18.3.4.1. No Symmetry 18.3.4.2. Horizontal Symmetry 18.3.4.3. Vertical Symmetry 18.3.4.4. Horizontal and Vertical Symmetry 18.3.4.5. Diagonal Symmetry
19. Frame Cleaner Intel® FPGA IP x
19.1. About the Frame Cleaner IP 19.2. Frame Cleaner IP Parameters 19.3. Frame Cleaner IP Functional Description 19.4. Frame Cleaner IP Interfaces 19.5. Frame Cleaner IP Registers 19.6. Frame Cleaner IP Software API
19.1. About the Frame Cleaner IP x
19.1.1. Frame Cleaner IP Performance and Resources
20. Full-Raster to Clocked Video Converter Intel® FPGA IP x
20.1. About the Full-Raster to Clocked Video Converter 20.2. Full Raster to Clocked Video Converter Parameters 20.3. Full-Raster to Clocked Video Converter Block Description 20.4. Full-Raster to Clocked Video Converter Registers
20.1. About the Full-Raster to Clocked Video Converter x
20.1.1. Full-Raster to Clocked Video Converter Features 20.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
20.3. Full-Raster to Clocked Video Converter Block Description x
20.3.1. Full Raster to Clocked Video Converter Interfaces
21. Full-Raster to Streaming Converter Intel® FPGA IP x
21.1. About the Full-Raster to Streaming Converter IP 21.2. Full-Raster to Streaming Converter Parameters 21.3. Full-Raster to Streaming Converter Block Description
21.1. About the Full-Raster to Streaming Converter IP x
21.1.1. Full-Raster to Streaming Converter Features 21.1.2. Full-Raster to Streaming Converter Performance and Resources
21.3. Full-Raster to Streaming Converter Block Description x
21.3.1. Full-Raster to Streaming Converter Interfaces
22. Genlock Controller Intel® FPGA IP x
22.1. About the Genlock Controller IP 22.2. Genlock Controller IP Parameters 22.3. Genlock Controller IP Functional Description 22.4. Using Genlock Controller IP Software 22.5. Genlock Controller IP Registers 22.6. Genlock Controller IP Software API
22.1. About the Genlock Controller IP x
22.1.1. Genlock Controller IP Performance and Resources
22.3. Genlock Controller IP Functional Description x
22.3.1. Genlock Controller IP Interfaces
22.4. Using Genlock Controller IP Software x
22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 22.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 22.4.3. Setting the VCXO hold over 22.4.4. Restarting the Genlock Controller IP 22.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 22.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 22.4.7. Disturbing a Reference Clock (a cable pull)
23. Generic Crosspoint Intel® FPGA IP x
23.1. About the Generic Crosspoint IP 23.2. Generic Crosspoint IP Parameters 23.3. Generic Crosspoint IP Interfaces 23.4. Generic Crosspoint IP Registers 23.5. Generic Crosspoint IP Software API
23.1. About the Generic Crosspoint IP x
23.1.1. Generic Crosspoint IP Features 23.1.2. Generic Crosspoint Performance and Resources
24. Genlock Signal Router Intel® FPGA IP x
24.1. About the Genlock Signal Router IP 24.2. Genlock Signal Router IP Parameters 24.3. Genlock Signal Router IP Interfaces 24.4. Genlock Signal Router IP Registers 24.5. Genlock Signal Router IP Software API
24.1. About the Genlock Signal Router IP x
24.1.1. Genlock Signal Router IP Features 24.1.2. Genlock Signal Router IP Performance and Resources
25. Guard Bands Intel® FPGA IP x
25.1. About the Guard Bands IP 25.2. Guard Bands IP Parameters 25.3. Guard Bands IP Interfaces 25.4. Guard Bands IP Registers 25.5. Guard Bands IP Software API
25.1. About the Guard Bands IP x
25.1.1. Guard Bands IP Performance and Resources
26. Interlacer Intel® FPGA IP x
26.1. About the Interlacer IP 26.2. Interlacer IP Parameters 26.3. Interlacer IP Functional Description 26.4. Interlacer IP Registers 26.5. Interlacer IP Software API
26.1. About the Interlacer IP x
26.1.1. Interlacer IP Performance and Resources
26.3. Interlacer IP Functional Description x
26.3.1. Interlacer IP Interfaces
27. Mixer Intel® FPGA IP x
27.1. About the Mixer IP 27.2. Mixer IP Parameters 27.3. Mixer IP Functional Description 27.4. Mixer IP Registers 27.5. Mixer IP Software API
27.1. About the Mixer IP x
27.1.1. Mixer IP Performance and Resources
27.3. Mixer IP Functional Description x
27.3.1. Mixer IP Interfaces
28. Pixels in Parallel Converter Intel® FPGA IP x
28.1. About the Pixels in Parallel Converter IP 28.2. Pixels in Parallel Converter IP Parameters 28.3. Pixels in Parallel Converter Interfaces 28.4. Pixels in Parallel Converter Registers 28.5. Pixels in Parallel Converter IP Software API
28.1. About the Pixels in Parallel Converter IP x
28.1.1. Pixels in Parallel Converter IP Performance and Resources
29. Scaler Intel® FPGA IP x
29.1. About the Scaler 29.2. Scaler IP Parameters 29.3. Scaler IP Functional Description 29.4. Scaler IP Registers 29.5. Scaler IP Software API
29.1. About the Scaler x
29.1.1. Scaler IP Performance and Resources
29.2. Scaler IP Parameters x
29.2.1. Scaler Maximum Resolution
29.3. Scaler IP Functional Description x
29.3.1. Coefficient Selection 29.3.2. Coefficient Quantization 29.3.3. Partial Frame Scaling 29.3.4. 422 and 420 Chroma Sampled Data Scaling 29.3.5. Scaler IP Interfaces
29.3.1. Coefficient Selection x
29.3.1.1. Updating Scaler IP Runtime Coefficients
30. Stream Cleaner Intel® FPGA IP x
30.1. About the Stream Cleaner IP 30.2. Stream Cleaner IP Parameters 30.3. Stream Cleaner IP Functional Description
30.1. About the Stream Cleaner IP x
30.1.1. Stream Cleaner IP Performance and Resources
30.3. Stream Cleaner IP Functional Description x
30.3.1. Stream Cleaner IP Interfaces
31. Switch Intel® FPGA IP x
31.1. About the Switch IP 31.2. Switch IP Parameters 31.3. Switch IP Functional Description 31.4. Switch IP Registers 31.5. Switch IP Software API
31.1. About the Switch IP x
31.1.1. Switch IP Performance and Resources
31.3. Switch IP Functional Description x
31.3.1. Switch IP Latency 31.3.2. Switch IP Interfaces
32. Tone Mapping Operator Intel® FPGA IP x
32.1. About the Tone Mapping Operator IP 32.2. TMO IP Parameters 32.3. TMO IP Block Description 32.4. TMO IP Registers 32.5. TMO IP Software API
32.1. About the Tone Mapping Operator IP x
32.1.1. TMO IP Features 32.1.2. TMO IP Performance and Resource Utilization
32.3. TMO IP Block Description x
32.3.1. TMO IP Interfaces 32.3.2. TMO IP Latency
33. Test Pattern Generator Intel® FPGA IP x
33.1. About the Test Pattern Generator IP 33.2. Test Pattern Generator IP Parameters 33.3. Test Pattern Generator IP Functional Description 33.4. Test Pattern Generator IP Registers 33.5. Test Pattern Generator IP Software API
33.1. About the Test Pattern Generator IP x
33.1.1. Test Pattern Generator IP Performance and Resources
33.3. Test Pattern Generator IP Functional Description x
33.3.1. Test Pattern Generator IP Interfaces
34. Video Frame Buffer Intel® FPGA IP x
34.1. About the Video Frame Buffer IP 34.2. Video Frame Buffer IP Parameters 34.3. Video Frame Buffer IP Functional Description 34.4. Video Frame Buffer IP Registers 34.5. Video Frame Buffer IP Software API
34.1. About the Video Frame Buffer IP x
34.1.1. Video Frame Buffer Performance and Resources
34.3. Video Frame Buffer IP Functional Description x
34.3.1. Video Frame Buffer IP Interfaces
35. Video Streaming FIFO Intel® FPGA IP x
35.1. About the Video Streaming FIFO IP 35.2. Video Streaming FIFO IP Parameters 35.3. Video Streaming FIFO IP Interfaces
35.1. About the Video Streaming FIFO IP x
35.1.1. Video Streaming FIFO IP Performance and Resources
36. Video Timing Generator Intel® FPGA IP x
36.1. About the Video Timing Generator IP 36.2. Video Timing Generator IP Parameters 36.3. Video Timing Generator IP Functional Description 36.4. Video Timing Generator IP Interfaces 36.5. Video Timing Generator IP Registers 36.6. Video Timing Generator IP Software API
36.1. About the Video Timing Generator IP x
36.1.1. Video Timing Generator IP Features 36.1.2. Video Timing Generator IP Performance and Resources
37. Warp Intel® FPGA IP x
37.1. About the Warp IP 37.2. Warp IP Parameters 37.3. Warp IP Block Description 37.4. Warp IP Registers 37.5. Warp IP Software API
37.1. About the Warp IP x
37.1.1. Warp IP Features 37.1.2. Warp IP Performance and Resource Utilization
37.3. Warp IP Block Description x
37.3.1. Block Cache Tool 37.3.2. Warp IP Interfaces 37.3.3. Warp IP Latency 37.3.4. External Memory for Warp IP
37.5. Warp IP Software API x
37.5.1. Using Warp IP Software 37.5.2. Warp IP Software Code Examples
38. Design Security x
38.1. Memory Subsystems 38.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Key Intel® FPGA IP
11. Chroma Resampler Intel® FPGA IP
12. Clipper Intel® FPGA IP
13. Clocked Video Input Intel® FPGA IP
14. Clocked Video to Full-Raster Converter Intel® FPGA IP
15. Clocked Video Output Intel® FPGA IP
16. Color Space Converter Intel® FPGA IP
17. Deinterlacer Intel® FPGA IP
18. FIR Filter Intel® FPGA IP
19. Frame Cleaner Intel® FPGA IP
20. Full-Raster to Clocked Video Converter Intel® FPGA IP
21. Full-Raster to Streaming Converter Intel® FPGA IP
22. Genlock Controller Intel® FPGA IP
23. Generic Crosspoint Intel® FPGA IP
24. Genlock Signal Router Intel® FPGA IP
25. Guard Bands Intel® FPGA IP
26. Interlacer Intel® FPGA IP
27. Mixer Intel® FPGA IP
28. Pixels in Parallel Converter Intel® FPGA IP
29. Scaler Intel® FPGA IP
30. Stream Cleaner Intel® FPGA IP
31. Switch Intel® FPGA IP
32. Tone Mapping Operator Intel® FPGA IP
33. Test Pattern Generator Intel® FPGA IP
34. Video Frame Buffer Intel® FPGA IP
35. Video Streaming FIFO Intel® FPGA IP
36. Video Timing Generator Intel® FPGA IP
37. Warp Intel® FPGA IP
38. Design Security
39. Document Revision History for Video and Vision Processing Suite User Guide

15.5. Clocked Video Output IP Registers

The Clocked Video Output IP allows runtime configuration of parameters via Avalon memory-mapped processor register interface. The processor interface is optional. You turn it on at build time in the CVO Configuration GUI. Unless stated, all registers are 32-bit wide.

The address space is split into two regions. Addresses 0x140-0x194 are reserved for the core Clocked Video Output IP registers. Addresses 0x240-0x2FC are reserved for the optional internal Video Timing Generator. If you use the external AXI4-S full-raster input, registers 0x240-0x2FC are read only and return 0x1234abcd.

Table 198.   Parameterization Registers
Register Offset Access Description
Clocked Video Output Parameterization Registers
VID_PID 0x000 RO Read this register to retrieve clocked video output IP product ID
VERSION 0x004 RO Read this register to retrieve the version information for the Intel Quartus release that Intel uses to build the Clocked Video Output IP
VID_FIFO_DEPTH 0x008 RO The depth of the video input cdc fifo.
TPG_FIFO_DEPTH 0x00c RO The depth of the test pattern input cdc fifo.
BPS 0x010 RO The bits per video sample
INTERNAL_VTIMING 0x014 RO

If ‘1’, the IP includes an internal video timing generator.

If ‘0’, and external video timing generator is required.
FALL_BACK_INPUT_EN 0x018 RO If ‘1’, the second video input has been enabled.
PIXELS_IN_PARALLEL 0x01c RO The number of pixels per clock transferred on the AXI4-S busses.
NUMBER_OF_COLOR_PLANES 0x020 RO The number of color planes per pixel
SEPARATE_SLAVE_CLOCK 0x024 RO This returns ‘1’ because the processor interface always uses a separate clock.
CPU_CLK_FREQ_HZ 0x028 RO The frequency, in Hz, of the processor interface clock.
TIM_DIMENSIONS 0x02c RO

If set to ‘1’, the processor Interface diagnostics include the dimensions of the input timing reference.

If 0, the dimensions of the timing reference are not available to the processor interface.
VID_IS_ASYNC 0x030 RO

If 1, the video input is treated as asynchronous to the timing reference.

If 0, the video input must use the AXI4-S full-raster video clock
VID_DIMENSIONS 0x034 RO

If 1, the processor interface diagnostics include the dimensions of the video input.

If 0, the dimensions of the video input are not available to the processor interface.
VID_DEBUG 0x038 RO

If 1, the processor Interface diagnostics include the locked, size err, and stall counters for the video input.

If 0, the counters are not available to the processor Interface
TPG_IS_ASYNC 0x03c RO

If 1, the test pattern input is treated as asynchronous to the timing reference.

If 0, the test pattern input must use the AXI4-S full-raster video clock
TPG_DIMENSIONS 0x040 RO

If 1, the processor interface diagnostics include the dimensions of the test pattern input.

If 0, the dimensions of the test pattern input are not available to the processor interface.
TPG_DEBUG 0x044 RO

If 1, the processor Interface diagnostics include the locked, size err, and stall counters for the test pattern input.

If 0, the counters are not available to the processor Interface

Video Timing Generator Parameterization Registers

These registers only exist if register 0x014 “INTERNAL_VTIMING” returns True.

NUM_PULSES 0x048 RO The number of additional output pulses generated by the internal Video Timing Generator.
HSIZE 0x04c RO The number of bits used to build the horizontal counters and comparators inside the Video Timing Generator. This determines the maximum width of raster that can be generated.
VSIZE 0x050 RO The number of bits used to build the vertical counters and comparators inside the Video Timing Generator. This determines the maximum height of raster that can be generated.
BUILD_HARD_FRAME_LOCK 0x054 RO

If true, the internal Video Timing Generator includes the Hard Frame Lock function.

If false, the internal Video Timing Generator cannot “hard lock” to an external reference.

BUILD_SOFT_FRAME_LOCK 0x058 RO

If true, the internal Video Timing Generator includes the Soft Frame Lock function.

If false, the internal Video Timing Generator cannot “soft lock” to an external reference.

BUILD_VRR 0x05c RO

If true, the internal Video Timing Generator includes the Variable Refresh Rate.

If false, the internal Video Timing Generator cannot generate a variable refresh rate.
Table 199.   Clocked Video Output Core Registers The core registers control the operation of the Clocked Video Output IP. They include optional diagnostic registers that assist with system development.
Register Offset Access Description
REG_STATUS 0x140 RO Returns the status of the merge process.
REG_BLACK_0 0x144 RW The initial value of “black” for this color plane
REG_BLACK_1 0x148 RW 33 The initial value of “black” for this color plane
REG_BLACK_2 0x14c RW 33 The initial value of “black” for this color plane
REG_BLACK_3 0x150 RW 33 The initial value of “black” for this color plane
REG_FALLBACK 0x154 RW Defines the behavior of the merge block if the video input fails
REG_FR_H_DIMS 0x158 RO 34 The active and total widths of the AXI4-S full-raster Timing Input
REG_FUR_V_DIMS 0x15c RO 34 The active and total heights of the AXI4-S full-raster Timing Input
REG_FR_FULL RASTEREQ_DIMS 0x160 RO 34 The frequency, in Hz, of the AXI4-S full-raster clock
REG_FR_CLKS_DIMS 0x164 RO34 The number of AXI4-S full-raster clocks per input frame.
REG_VID_DIMS 0x168 RO 34 The active height and width of the video input.
REG_VID_FREQ_DIMS 0x16c RO 34 The frequency, in Hz, of the video input clock
REG_VID_CLKS_DIMS 0x170 RO 34 The number of video input clocks per input frame.
REG_TPG_DIMS 0x174 RO 34 The active height and width of the test pattern input.
REG_TPG_FREQ_DIMS 0x178 RO 34 The frequency, in Hz, of the test pattern input clock
REG_TPG_CLKS_DIMS 0x17c RO 34 The number of test pattern input clocks per input frame.
REG_VID_LOCKED_COUNT 0x180 RO 34 Diagnostic counter that increments once at the start of each locked video frame.
REG_VID_SIZE_ERR_COUNT 0x184 RO 34 Diagnostic counter that increments every time a mismatch between the video input and timing input is detected.
REG_VID_STALL_COUNT 0x188 RO 34 Diagnostic counter that increments every time the video input stalls and is dropped by the merge block.
REG_TPG_LOCKED_COUNT 0x18c RO 34 Diagnostic counter that increments once at the start of each locked test pattern frame.
REG_TPG_SIZE_ERR_COUNT 0x190 RO 34 Diagnostic counter that increments every time a mismatch between the test pattern input and timing input is detected.
REG_TPG_STALL_COUNT 0x194 RO 34 Diagnostic counter that increments every time the test pattern input stalls and is dropped by the merge block.

Register Bit Descriptions

Table 200.  REG_STATUS
Name Bits Attribute Description
VID_LOCKED 0 RO

When ‘1’, the video input is locked with the timing reference

When ‘0’, the IP is waiting to achieve “lock” between the video input and the timing reference.

VID_AXI4-S_FULL 1 RO

When ‘1’, the IP has detected the video input is an AXI4-S Full stream

When ‘0’, the IP has detected the video input is an AXI4-S Lite stream

VID_STALL_ERR 2 RO

When ‘1’, the video input has stalled (dropped it’s tValid) when the timing reference has required active pixels.

When ‘0’, the video input is supplying pixels at the required pixel rate.

VID_SIZE_ERR 3 RO

When ‘1’, the active dimensions of the video input do not match the active dimensions of the timing reference.

When ‘0’, the active dimensions of the video input and the timing reference match.

TPG_LOCKED 4 RO

When ‘1’, the test pattern input is locked with the timing reference

When ‘0’, the IP is waiting to achieve “lock” between the test pattern input and the timing reference.

TPG_AXI4-S_FULL 5 RO

When ‘1’, the IP has detected the test pattern input is an AXI4-S Full stream

When ‘0’, the IP has detected the test pattern input is an AXI4-S Lite stream

TPG_STALL_ERR 6 RO

When ‘1’, the test pattern input has stalled (dropped it’s tValid) when the timing reference has required active pixels.

When ‘0’, the test pattern input is supplying pixels at the required pixel rate.

TPG_SIZE_ERR 7 RO

When ‘1’, the active dimensions of the test pattern input do not match the active dimensions of the timing reference.

When ‘0’, the active dimensions of the test pattern input and the timing reference match.

TIMING_PHASE 11:8 RO If there are 2 or more Pixels in Parallel, this indicates where the first active pixel occurred for the current line.
Reserved 31:12 Rsvd Reserved
Table 201.  REG_BLACK_0
Name Bits Attribute Description
BLACK_0 BIT_DEPTH-1:0 RW The initial value of “black” for this color plane
Table 202.  REG_BLACK_1
Name Bits Attribute Description
BLACK_1 BIT_DEPTH-1:0 RW

The initial value of “black” for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist

Table 203.  REG_BLACK_2
Name Bits Attribute Description
BLACK_2 BIT_DEPTH-1:0 RW

The initial value of “black” for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist

Table 204.  REG_BLACK_3
Name Bits Attribute Description
BLACK_3 BIT_DEPTH-1:0 RW

The initial value of “black” for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist

Table 205.  REG_FALLBACK
Name Bits Attribute Description
Auto Recover 0 RW

If the input video is dropped due to an error, then when this bit is ‘1’ the IP automatically returns to the video input once it is relocked

If ‘0’, the IP does not automatically return to the video input following an error, and you must manually switch using the “recover now” register bit.

Force Black 1 RW If ‘1’, the IP is forced to output the Clocked Video Output IP Black values.
Force TPG 2 RW If ‘1’, the IP is forced to output the Test Pattern video input.
Force Video 3 RW If ‘1’, the IP is forced to output the video input.
Reserved 30:4 Rsvd Reserved
Recover Now 31 W1R0

This register bit self-clears.

Write a ‘1’ to this bit to force the IP to return to the video input if the video input is valid.

Writing a ‘0’ has no effect.

Table 206.  REG_FR_H_DIMS
Name Bits Attribute Description
hTotal 15:0 RO Returns the detected total width of the timing reference.
hActive 31:16 RO Returns the detected active width of the timing reference.
Table 207.  REG_FR_V_DIMS
Name Bits Attribute Description
vTotal 15:0 RO Returns the detected total height of the timing reference.
vActive 31:16 RO Returns the detected active height of the timing reference.
Table 208.  REG_FR_FREQ_DIMS
Name Bits Attribute Description
Clock Frequency 31:0 RO The frequency, in Hz, of the AXI4-S full-raster clock
Table 209.  REG_FR_CLKS_DIMS
Name Bits Attribute Description
Frame Period 31:0 RO The number of AXI4-S full-raster clocks per input frame.
Table 210.   REG_VID_DIMS
Name Bits Attribute Description
hActive 15:0 RO The detected active with of the video input.
vActive 31:16 RO The detected active height of the video input
Table 211.  REG_VID_FREQ_DIMS
Name Bits Attribute Description
Clock Frequency 31:0 RO The frequency, in Hz, of the video input clock
Table 212.  REG_VID_CLKS_DIMS
Name Bits Attribute Description
Frame Period 31:0 RO The number of video input clocks per input frame.
Table 213.   REG_TPG_DIMS
Name Bits Attribute Description
hActive 15:0 RO The detected active with of the test pattern input.
vActive 31:16 RO The detected active height of the test pattern input
Table 214.  REG_TPG_FREQ_DIMS
Name Bits Attribute Description
Clock Frequency 31:0 RO The frequency, in Hz, of the test pattern input clock
Table 215.  REG_TPG_CLKS_DIMS
Name Bits Attribute Description
Frame Period 31:0 RO The number of test pattern input clocks per input frame.
Table 216.  REG_VID_LOCKED_COUNT
Name Bits Attribute Description
Locked Count 31:0 RO Diagnostic counter that increments once at the start of each locked video frame.
Table 217.  REG_VID_SIZE_ERR_COUNT
Name Bits Attribute Description
Size Error Count 31:0 RO Diagnostic counter that increments every time a mismatch between the video input and timing input is detected.
Table 218.  REG_VID_STALL_COUNT
Name Bits Attribute Description
Stall Count 31:0 RO Diagnostic counter that increments every time the video input stalls and is dropped by the merge block.
Table 219.  REG_TPG_LOCKED_COUNT
Name Bits Attribute Description
Locked Count 31:0 RO Diagnostic counter that increments once at the start of each locked test pattern input frame.
Table 220.  REG_TPG_SIZE_ERR_COUNT
Name Bits Attribute Description
Size Error Count 31:0 RO Diagnostic counter that increments every time a mismatch between the test pattern input and timing input is detected.
Table 221.  REG_TPG_STALL_COUNT
Name Bits Attribute Description
Stall Count 31:0 RO Diagnostic counter that increments every time the test pattern input stalls and is dropped by the merge block.

Video Timing Generator Registers

The Clocked Video Output IP includes an optional internal Video Timing Generator IP. The Video Timing Generator IP processor registers start at address offset 0x240.

The offset to the Video Timing Generator IP registers is different when you use them in the Clocked Video Output IP, compared to standalone.

Table 222.  Video Timing Generator Registers
Register Offset Access Description

Raster Timing Registers

REG_STATUS 0x240 RO Reserved
REG_COMMIT 0x244 RW Update internal parameters with new video standard.
REG_MODE 0x248 RW Control mode of operation.
REG_RESET_POS 0x24c RW Expected position of the start of frame input signal, relative to the raster
REG_TOTALS 0x250 RW Total height and width of the raster
REG_HB_END 0x254 RW First active pixel of a line
REG_V1B_POS 0x258 RW Start and end of vertical blanking for field 1
REG_V2B_POS 0x25c RW Start and end of vertical blanking for field 2
REG_FIELD_STARTS 0x260 RW First lines of field 1 and 2
REG_HS_POS 0x264 RW The start and end of horizontal sync
REG_V1S_START 0x268 RW The horizontal and vertical position of the start of the vertical sync for field 1
REG_V1S_END 0x26c RW The horizontal and vertical position of the end of the vertical sync for field 1
REG_V2S_START 0x270 RW The horizontal and vertical position of the start of the vertical sync for field 2
REG_V2S_END 0x274 RW The horizontal and vertical position of the end of the vertical sync for field 2
REG_JITTER_CONT 0x278 RW Timing parameters for the hard and soft frame lock
REG_BLACK_0 0x27c RW The initial value of “black” for this color plane
REG_BLACK_1 0x280 RW33 The initial value of “black” for this color plane
REG_BLACK_2 0x284 RW33 The initial value of “black” for this color plane
REG_BLACK_3 0x288 RW33 The initial value of “black” for this color plane
REG_FRAME_COUNTS 0x28c RO Returns the total number of frames output, and the number of external frame starts received.
REG_FRAME_LENGTH 0x290 RO The number of video clocks between consecutive frame start input signals
REG_VTOTAL_ADJ 0x294 RO35 The total height of the raster after adjustment for soft Lock.
REG_VID_FREQ 0x298 RO The frequency of the video clock, in Hz.
REG_GENLOCK_STATS0 0x29c RO Diagnostics for hard and soft frame lock
REG_GENLOCK_STATS1 0x2a0 RO Diagnostics for Soft frame lock.

Pulse and Toggle Timing Registers

REG_PULSE0_START 0x2c0 RW 36 The horizontal and vertical position of the start of the pulse
REG_PULSE0_END 0x2c4 RW 36 The horizontal and vertical position of the end of the pulse
REG_PULSE1_START 0x2c8 RW36 The horizontal and vertical position of the start of the pulse
REG_PULSE1_END 0x2cc RW36 The horizontal and vertical position of the end of the pulse
REG_PULSE2_START 0x2d0 RW36 The horizontal and vertical position of the start of the pulse
REG_PULSE2_END 0x2d4 RW36 The horizontal and vertical position of the end of the pulse
REG_PULSE3_START 0x2d8 RW36 The horizontal and vertical position of the start of the pulse
REG_PULSE3_END 0x2dc RW36 The horizontal and vertical position of the end of the pulse
REG_PULSE4_START 0x2e0 RW36 The horizontal and vertical position of the start of the pulse
REG_PULSE4_END 0x2e4 RW36 The horizontal and vertical position of the end of the pulse
REG_PULSE5_START 0x2e8 RW36 The horizontal and vertical position of the start of the pulse
REG_PULSE5_END 0x2ec RW36 The horizontal and vertical position of the end of the pulse
REG_PULSE6_START 0x2f0 RW36 The horizontal and vertical position of the start of the pulse
REG_PULSE6_END 0x2f4 RW36 The horizontal and vertical position of the end of the pulse
REG_PULSE7_START 0x2f8 RW36 The horizontal and vertical position of the start of the pulse
REG_PULSE7_END 0x2fc RW36 The horizontal and vertical position of the end of the pulse
33

This register is RO and returns 0x1234abcd if the color plane does not exist

34

This register is optional. If turned off on the CVO Configuration GUI, this register returns 0x1234abcd

35

If Soft Mode is turned off, this register is undefined.

36

This register is RO and returns 0x1234abcd if the pulse does not exist. Refer to the Number of pulses parameter.

Level Two Title