Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

3.3. IP Debugging Features

If you turn on Memory-mapped control interface for a video and vision processing IP, you can also turn on Debug features.

For lite variants with Debug features on, you can read back any values you write to the control IMG_INFO registers.

Debugging features with full variants allow you to query details of received image information packets. Every time an IP receives an image information packet, the image information fields are stored in a debug IMG_INFO register bank. You can read back this information over the memory-mapped control interface.

In a system that is not behaving as expected the debugging features are a useful debugging tool. If required, when the system is working, the IP can be regenerated in Platform Designer with debugging features off so that the design does not add the area cost of the debugging register bank.

Table 4.  Relative ALM consumption for full variant, lite variant, and debug features (Clipper IPs)The table shows the relative ALM consumption of the clipper IP, with and without debugging features. The clipper parameters are 2 pixels in parallel, 8 bits per color sample, 2 color planes and clipping with offsets. For comparison, the table includes the lite variant Clipper and the VIP Clipper II IP. The table includes timing slack for a clocking target of 333 MHz. The designs use default settings, the Intel Quartus Prime Pro edition version 21.4, and target a Cyclone 10 GX 10CX220YF78015G device The table shows debugging features slightly affect fMAX.
IP ALMs Slack when targeting 333 MHz (ns)
Clipper IP (full) 493 0.481
Clipper IP (full with debug features) 616 0.494
Clipper IP (lite) 394 0.451
VIP Clipper II 670 0.359
Table 5.  Relative timing slack for Clipper IPsThe table shows an artificially aggressive target frequency for the Clipper IP for an Intel Cyclone 10 device of 525 MHz. Turning on Debug features reduces Fmax to 518 MHz. For comparison with a full variant clipper, the table includes a lite variant Clipper and the VIP Clipper II IP. All figures using default settings with Intel Quartus Prime Pro edition release 21.4, targeting an Intel Cyclone 10 GX 10CX220YF78015G device
IP ALMs Slack when targeting 525 MHz
ns MHz
Clipper IP (full variant) 494 0.001 525
Clipper IP (full variant with debug features) 614 -0.028 518
Clipper IP (lite variant) 395 0.065 545
VIP Clipper II 672 -0.659 390