Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

34.1. About the Video Frame Buffer IP

The IP buffers frames of video and can perform frame dropping and repeating to double or triple buffer frames. The IP stores frames in external memory, so the frame buffer has Avalon memory-mapped interfaces to allow connection to an external memory interface.

The frame buffer supports:

  • Triple or double buffering for progressive video frames
  • Double buffering for interlaced video fields
  • Auxiliary control packets. Local storage for up to 255. The IP can optionally drop and repeat auxiliary packets with their associated frame.
  • Maximum frame resolutions of 16384 by 16384 pixels with 1 to 8 pixels in parallel and any color space
  • Configurable memory packing scheme
  • Optional dropping of broken frames
  • Frame statistics counters

The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. The Video Frame Buffer IP takes input resolution information from image information packets or extracts it using the register interface for lite variants.

An Avalon memory-mapped interface allows you to read frame statistics and turn the frame buffer output off and on at run time. You must have this interface for lite variants.

For details about latency and reset behavior for the Video Frame Buffer, refer to Video and Vision IPs Functional Description.