Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

15.3. Clocked Video Output IP Functional Description

The IP includes a merge block, which monitors the timing bus. It does not push back on the timing bus. The merge block stalls the video pixel data bus and test pattern generator pixel data bus when it sees the start of frame on the pixel data bus. The IP releases the pixel data buses when the timing bus contains the start of active pixel data.

Diagnostics report the status of the merge block via discreet output pins and the processor Interface.

Figure 36. External Timing Reference Bus
Figure 37. Embedded Video Timing Generator

The IP has a build-time option to include or exclude the tReady signal for the AXI4-S full-raster interface. The IP does not use this signal, but it allows you to connect to an AXI4-S full-raster bus that includes this signal. If the tReady signal is deasserted, the Clocked Video Output IP continues to output data.

The Clocked Video Output IP produces output on the transmit clock for the connectivity IP.

The processor interface operates on the processor clock domain. Intel recommends that you drive the processor Interface from a known stable clock, such as a dedicated processor clock. Do not drive with the transmit clock for the connectivity IP, which can be unstable. For example when standards change, the transmit clock can be unstable. If you use the transmit clock to clock the processor interface it can potentially corrupt the processor interface.