Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

24.1. About the Genlock Signal Router IP

The IP is a multichannel genlock strobe extractor and router. This IP passes genlock timing signals to internal or external FPGA multirate video clock generators. The IP helps video input and output clock genlock and frame synchronization, based on video timing markers derived from video connectivity IPs.
Figure 59. Genlock Signal Router IP Block Diagram

Data is input to and output from the Genlock Signal Router IP via a selectable number of ports. The final number of input and output ports, which is in the range 1 through 32 inclusive, can be configured via a Genlock Signal Router IP GUI.

At build time, you can configure the input port interfaces in three different modes: Intel video streaming full-raster, Intel clocked video, and clock only mode. The IP automatically extracts timing information from the input signals, and then routes the signals between the input and output ports. You can control the input-to-output routing dynamically at run-time using the processor interface.

The output interface for this IP provides two optional interfaces:

  • An interface with a set of discrete timing signals, such as field flag, horizontal, and vertical synchronization timing markers.
  • An interface that provides clocks only ports

The timing markers can then pass to internal or external FPGA multirate video clock generators.