Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

8.3. 3D LUT IP Block Description

The 3D LUT IP accepts RGB-format video input from its Intel FPGA video streaming interface. It uses the most significant bits (MSBs) of the 3 color component inputs to retrieve data values from the contents of the LUT and the least significant bits (LSBs) to interpolate the final output value. An Avalon Memory-Mapped compatible CPU interface handles the run-time control and LUT programming.
Figure 14. 3D LUT IP block diagram

The address decoder converts the MSBs of the three input color components into read addresses for the LUT. If you turn on Double buffered, the IP adds a page offset to the address when selecting the second buffer via the CPU interface. Page-flip double buffering allows for instantaneous switching between LUTs.

The LUT RAM instantiates the on-chip memory containing the LUT. The 3D LUT cube vertices are divided across eight sub-RAMs to output the target sub-cube vertices in parallel. Enabling the second buffer doubles the memory depth of the LUT. Both buffers' contents are programmable via the CPU interface and can also be pre-initialized in the firmware via the 3D LUT IP GUI.

The tetrahedral interpolator uses a DSP-efficient method to interpolate four of the LUT subcube vertices using the input LSBs. Part of the input MSBs determines which of the six tetrahedra in the target sub-cube contains the pixel.

The control register in the run-time control register map allows you to switch between the interpolated output and the bypass output.

Consider these points when integrating into a streaming video pipeline:

  • The IP controls buffer selection and output enable and only updates them at the start of each new frame.
  • The internal pipeline forwards control signals and is unaffected by changes to video resolution.
Figure 15. 3D LUT color transform examplesFrom top left: original, saturation, brightness increase, colorize (purple), colorize (green), desaturation