Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/12/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

1.4. Lite versus Full IP Variants

Most video and vision processing IPs support both full and lite variants of the Intel FPGA streaming video protocol. You should choose which protocol variant (and therefore which parameterization of the IPs) is most suitable for your end application. The Warp, 3D LUT, and TMO IPs only use the lite variant of the protocol. Therefore, they do not pass control information along the streaming interface.

For the full variants, the IPs transmit some control information together with video data over the streaming interfaces. For the lite variants, write all the control information to IPs using a processor interface.

You may still select run-time control via a processor interface when using the full variant of IPs (for example to update clipper offsets or mixer settings). The control information about the size and type of incoming video is always handled automatically using streamed control packets.

You can turn on or off lite mode in the GUI for most of the Intel video and vision processing IPs. When off, the IP is a full variant. You can interface between full and lite variants of IPs using the protocol converter IP. However, system design is easier if a video pipeline standardizes on one version of the protocol.

When choosing between full and lite consider the following advantages:

For full IP variants:

  • Ease of use. Full variants of the IPs handle more of the system control aspects automatically.
  • Video and Image Processing Suite interoperability or upgradeability. Interfacing or modifying existing systems based around the Video and Image Processing Suite IPs to the full variants is easier, as these handle video in a similar way.

For lite IP variants:

  • Building a system primarily using one of the Warp, 3D LUT or TMO IPs or a system requiring interoperability with third-party AXI-Stream video steaming IP. The Warp, 3D LUT, and TMO IPs use the lite variant of the protocol and do not pass control along the streaming interface.
  • Device area. Expect to save 100-200 ALMs per IP for lite variants.
Figure 1. Full and lite benefits radar diagram For example, lite variants are better for device area (lower area).

Regenerate IPs with either version of the protocol and compare overall system fMAX and area before deciding.