Quartus® Prime Pro Edition User Guide: Design Compilation

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Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Compilation 2. Reducing Compilation Time 3. Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Using the Compilation Dashboard 1.3. Design Netlist Infrastructure 1.4. Using the Node Finder 1.5. Precompiled Component (PCC) Generation Flow 1.6. Analysis & Elaboration Flow 1.7. Design Synthesis 1.8. Design Place and Route 1.9. Incremental Optimization Flow 1.10. Fast Forward Compilation Flow 1.11. Full Compilation Flow 1.12. Compilation Monitoring Mode 1.13. Exporting Compilation Results 1.14. Integrating Other EDA Tools 1.15. Compiler Optimization Techniques 1.16. Synthesis Language Support 1.17. Synthesis Settings Reference 1.18. Fitter Settings Reference 1.19. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy 1.1.3. Compilation on a Compute Farm
1.3. Design Netlist Infrastructure x
1.3.1. DNI Netlist Five-Box Data Model
1.6. Analysis & Elaboration Flow x
1.6.1. Exploring the RTL Analyzer Design Hierarchy Browser Schematic Viewer Properties Viewer Tcl Console Object Finder 1.6.2. Use Case Examples
1.6.1. Exploring the RTL Analyzer x
Design Hierarchy Browser Schematic Viewer Properties Viewer Tcl Console Object Finder 1.6.1.1. Sweep Hints Viewer 1.6.1.2. Object Set Console 1.6.1.3. Module Interfaces 1.6.1.4. Bundled Instances 1.6.1.5. Auto-hide Unconnected Pins 1.6.1.6. Filtering Ports and Nets 1.6.1.7. Expand Connections
1.6.2. Use Case Examples x
1.6.2.1. Scripting Routine Tasks Using Tcl Commands 1.6.2.2. Traversing the Design Netlist Using Tcl Commands
1.7. Design Synthesis x
1.7.1. Preparing for Design Synthesis 1.7.2. Running Synthesis 1.7.3. Using Synopsys* Design Constraint (SDC) on RTL Files 1.7.4. Post-Synthesis Static Timing Analysis (STA) 1.7.5. Viewing Synthesis Reports 1.7.6. Viewing Synthesis Dynamic Report
1.7.2. Running Synthesis x
1.7.2.1. Preserving Registers During Synthesis 1.7.2.2. Preserving Signals for Monitoring and Debugging
1.7.3. Using Synopsys* Design Constraint (SDC) on RTL Files x
1.7.3.1. Registering the SDC-on-RTL SDC File 1.7.3.2. Applying the SDC-on-RTL Constraints 1.7.3.3. Inspecting SDC-on-RTL Constraints 1.7.3.4. Creating Constraints in SDC-on-RTL SDC Files 1.7.3.5. Using Entity-Based SDC-on-RTL Constraints 1.7.3.6. Types of SDC Files Used in the Quartus® Prime Software 1.7.3.7. Example: Using SDC-on-RTL Features
1.8. Design Place and Route x
1.8.1. Running the Fitter 1.8.2. Viewing Fitter Reports
1.8.1. Running the Fitter x
1.8.1.1. Fitter Commands 1.8.1.2. Disabling or Enabling Physical Synthesis Optimization
1.8.2. Viewing Fitter Reports x
1.8.2.1. Plan Stage Reports 1.8.2.2. Place Stage Reports 1.8.2.3. Route Stage Reports 1.8.2.4. Retime Stage Reports 1.8.2.5. Finalize Stage Reports
1.8.2.2. Place Stage Reports x
1.8.2.2.1. Global Signal Visualization Report
1.8.2.3. Route Stage Reports x
1.8.2.3.1. Global Router Congestion Hotspot Summary Report 1.8.2.3.2. Global Router Wire Utilization Map Report
1.9. Incremental Optimization Flow x
1.9.1. Concurrent Analysis During Synthesis or Fitting 1.9.2. Analyzing Compiler Snapshots 1.9.3. Validating Periphery (I/O) after the Plan Stage
1.9.2. Analyzing Compiler Snapshots x
1.9.2.1. Running Snapshot Viewer
1.9.2.1. Running Snapshot Viewer x
1.9.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.9.2.1.2. Analyzing Clocking with Snapshot Viewer 1.9.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.9.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.9.2.1.5. Analyzing Congestion with Snapshot Viewer
1.10. Fast Forward Compilation Flow x
1.10.1. Step 1: Run Register Retiming 1.10.2. Step 2: Review Retiming Results 1.10.3. Step 3: Run Fast Forward Compile 1.10.4. Step 4: Review Fast Forward Results 1.10.5. Step 5: Implement Fast Forward Recommendations 1.10.6. Retiming Restrictions and Workarounds
1.10.2. Step 2: Review Retiming Results x
1.10.2.1. Locate Critical Chains
1.10.3. Step 3: Run Fast Forward Compile x
1.10.3.1. Fast Forward Compile By Hierarchy 1.10.3.2. HyperFlex Settings
1.10.4. Step 4: Review Fast Forward Results x
1.10.4.1. Clock Fmax Summary Report 1.10.4.2. Fast Forward Details Report
1.11. Full Compilation Flow x
1.11.1. Full Compilation Flow with Temporary Optimization Mode
1.13. Exporting Compilation Results x
1.13.1. Exporting a Version-Compatible Compilation Database 1.13.2. Importing a Version-Compatible Compilation Database 1.13.3. Creating a Design Partition 1.13.4. Exporting a Design Partition 1.13.5. Reusing a Design Partition 1.13.6. Viewing Quartus Database File Information 1.13.7. Clearing Compilation Results
1.13.6. Viewing Quartus Database File Information x
1.13.6.1. QDB File Attribute Types
1.14. Integrating Other EDA Tools x
1.14.1. Generating a VQM Netlist for other EDA Tools
1.15. Compiler Optimization Techniques x
1.15.1. Compiler Optimization Modes 1.15.2. Allow Register Retiming 1.15.3. Automatic Gated Clock Conversion 1.15.4. Enable Intermediate Fitter Snapshots 1.15.5. Fast Preserve Option 1.15.6. Fractal Synthesis Optimization
1.15.6. Fractal Synthesis Optimization x
1.15.6.1. Enabling or Disabling Fractal Synthesis
1.16. Synthesis Language Support x
1.16.1. Verilog and SystemVerilog Synthesis Support 1.16.2. VHDL Synthesis Support
1.16.1. Verilog and SystemVerilog Synthesis Support x
1.16.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.16.1.2. Design Libraries 1.16.1.3. Verilog HDL Configuration 1.16.1.4. Initial Constructs and Memory System Tasks 1.16.1.5. Verilog HDL Macros
1.16.1.3. Verilog HDL Configuration x
1.16.1.3.1. Hierarchical Design Configurations
1.16.2. VHDL Synthesis Support x
1.16.2.1. VHDL Input Settings (Settings Dialog Box) 1.16.2.2. VHDL Standard Libraries and Packages 1.16.2.3. VHDL wait Constructs 1.16.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.17. Synthesis Settings Reference x
1.17.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Strategies to Reduce the Overall Compilation Time 2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 2.4. Reducing Placement Time 2.5. Reducing Routing Time 2.6. Reducing Static Timing Analysis Time 2.7. Setting Process Priority 2.8. Reducing Compilation Time Revision History
2.2. Strategies to Reduce the Overall Compilation Time x
2.2.1. Running the ECO Compilation Flow 2.2.2. Enabling Multi-Processor Compilation 2.2.3. Using Block-Based Compilation
2.2.2. Enabling Multi-Processor Compilation x
2.2.2.1. Processor Base Clock Frequency 2.2.2.2. Random Access Memory (RAM) 2.2.2.3. Storage
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
2.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
2.4. Reducing Placement Time x
2.4.1. Placement Effort Multiplier Settings
2.5. Reducing Routing Time x
2.5.1. Identifying Routing Congestion with the Chip Planner
2.5.1. Identifying Routing Congestion with the Chip Planner x
2.5.1.1. Areas with Routing Congestion 2.5.1.2. Congestion due to HDL Coding style
Answers to Top FAQs
1. Design Compilation
2. Reducing Compilation Time
3. Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Quartus® Prime Pro Edition User Guides

1.6.1. Exploring the RTL Analyzer

You can invoke the RTL Analyzer from the Elaborated checkpoint of the Analysis & Elaboration stage by clicking on the first magnifier icon in the compilation dashboard. For details about checkpoints, refer to the Analysis & Elaboration Flow.

The RTL Analyzer GUI has the following major components:

Figure 9. RTL Analyzer GUI
Note:

Before exploring your design in the RTL Analyzer, select your desired viewing modes in the Display settings by navigating to View > Display Settings menu. The Auto zoom to current selection and Auto expand to current selection modes are enabled by default in the Display settings. You can disable one or both of these modes. In the enabled mode, the object you select in the hierarchy browser gets automatically highlighted in the schematic viewer. The schematic viewer and hierarchy browser expands the current selected object's hierarchy and adjusts the view to ensure the object is visible. Disable both modes if you do not want your current view to change in the hierarchy browser and schematic viewer.

Figure 10. Display Settings
Note: RTL Analyzer automatically saves the last view of your design when you close it. So, when you relaunch the RTL Analyzer, the last view is restored, including the highlighted objects and nodes, and you can continue your work from where you left it previously. However, in the event you change your RTL design and recompile the project after exiting the RTL Analyzer, the saved view is invalidated and not restored.

Design Hierarchy Browser

The design hierarchy browser renders the design netlist five-box data model. The core elements of this data model are modules, instances, ports, instance ports, and nets. For more information about this data model, refer to DNI Netlist Five-Box Data Model.

All objects in the hierarchy are organized by the object type. For example, I/Os are grouped based on the direction.

Various GUI elements of the RTL analyzer are synchronized and respond to the objects within the Objects pane. For example, for the currently selected object in the hierarchy browser, the schematic viewer brings the object into focus with a highlight, the Tcl Console emits an equivalent Tcl command, and the Properties viewer provides relevant information about the object. You can cross-probe from selected objects in the netlist to the source where they were defined by right-clicking on an object and selecting Locate Node > Locate in Design File option in the context-sensitive menu. The source file displays in the Quartus main window showing the line that instantiates the object.

Figure 11. Cross-probing Selected Objects in the Netlist

Schematic Viewer

The schematic viewer represents the design elements, such as modules, instances, ports, instance ports, and nets, schematically within the viewer. The viewer reacts and updates to bring different objects into focus as you navigate through the netlist.

Properties Viewer

The Property pane provides information about assignments and SDC constraints attached to the selected object in the hierarchy browser. You can cross-probe to the definition of the assignment in the source file.

Figure 12. Property Viewer Showing Constraints

Tcl Console

The Tcl Console provides a robust scripting interface that reports issues and displays relevant Tcl commands for GUI actions. It allows you to traverse and analyze your design. As you type the Tcl commands, notice how the schematic viewer and the hierarchy browser respond accordingly.

Object Finder

The object finder helps in locating an object in the design netlist. You can refine your search based on the object type (instance, instance bus, inst_port, port, port_bus, net, and net_bus) and modules. For complicated designs, you can further use filters to refine your search.

The RTL Analyzer provides the following tools and functionality:

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