Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Compilation 2. Reducing Compilation Time 3. Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Using the Compilation Dashboard 1.3. Design Netlist Infrastructure 1.4. Using the Node Finder 1.5. Precompiled Component (PCC) Generation Flow 1.6. Analysis & Elaboration Flow 1.7. Design Synthesis 1.8. Design Place and Route 1.9. Incremental Optimization Flow 1.10. Fast Forward Compilation Flow 1.11. Full Compilation Flow 1.12. Compilation Monitoring Mode 1.13. Exporting Compilation Results 1.14. Integrating Other EDA Tools 1.15. Compiler Optimization Techniques 1.16. Synthesis Language Support 1.17. Synthesis Settings Reference 1.18. Fitter Settings Reference 1.19. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy 1.1.3. Compilation on a Compute Farm
1.3. Design Netlist Infrastructure x
1.3.1. DNI Netlist Five-Box Data Model
1.6. Analysis & Elaboration Flow x
1.6.1. Exploring the RTL Analyzer 1.6.2. Use Case Examples
1.6.1. Exploring the RTL Analyzer x
1.6.1.1. Sweep Hints Viewer 1.6.1.2. Object Set Console 1.6.1.3. Module Interfaces 1.6.1.4. Bundled Instances 1.6.1.5. Auto-hide Unconnected Pins 1.6.1.6. Filtering Ports and Nets 1.6.1.7. Expand Connections
1.6.2. Use Case Examples x
1.6.2.1. Scripting Routine Tasks Using Tcl Commands 1.6.2.2. Traversing the Design Netlist Using Tcl Commands
1.7. Design Synthesis x
1.7.1. Preparing for Design Synthesis 1.7.2. Running Synthesis 1.7.3. Using Synopsys* Design Constraint (SDC) on RTL Files 1.7.4. Post-Synthesis Static Timing Analysis (STA) 1.7.5. Viewing Synthesis Reports 1.7.6. Viewing Synthesis Dynamic Report
1.7.2. Running Synthesis x
1.7.2.1. Preserving Registers During Synthesis 1.7.2.2. Preserving Signals for Monitoring and Debugging
1.7.3. Using Synopsys* Design Constraint (SDC) on RTL Files x
1.7.3.1. Registering the SDC-on-RTL SDC File 1.7.3.2. Applying the SDC-on-RTL Constraints 1.7.3.3. Inspecting SDC-on-RTL Constraints 1.7.3.4. Creating Constraints in SDC-on-RTL SDC Files 1.7.3.5. Using Entity-Based SDC-on-RTL Constraints 1.7.3.6. Types of SDC Files Used in the Quartus® Prime Software 1.7.3.7. Example: Using SDC-on-RTL Features Targeting Pins of Top-level Instances Targeting Pins in Cells Targeting Pins Using Wildcards Example 4. Applying Constraints at Deeper Hierarchies
1.8. Design Place and Route x
1.8.1. Running the Fitter 1.8.2. Viewing Fitter Reports
1.8.1. Running the Fitter x
1.8.1.1. Fitter Commands 1.8.1.2. Disabling or Enabling Physical Synthesis Optimization
1.8.2. Viewing Fitter Reports x
1.8.2.1. Plan Stage Reports 1.8.2.2. Place Stage Reports 1.8.2.3. Route Stage Reports 1.8.2.4. Retime Stage Reports 1.8.2.5. Finalize Stage Reports
1.8.2.2. Place Stage Reports x
1.8.2.2.1. Global Signal Visualization Report
1.8.2.3. Route Stage Reports x
1.8.2.3.1. Global Router Congestion Hotspot Summary Report 1.8.2.3.2. Global Router Wire Utilization Map Report
1.9. Incremental Optimization Flow x
1.9.1. Concurrent Analysis During Synthesis or Fitting 1.9.2. Analyzing Compiler Snapshots 1.9.3. Validating Periphery (I/O) after the Plan Stage
1.9.2. Analyzing Compiler Snapshots x
1.9.2.1. Running Snapshot Viewer
1.9.2.1. Running Snapshot Viewer x
1.9.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.9.2.1.2. Analyzing Clocking with Snapshot Viewer 1.9.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.9.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.9.2.1.5. Analyzing Congestion with Snapshot Viewer
1.10. Fast Forward Compilation Flow x
1.10.1. Step 1: Run Register Retiming 1.10.2. Step 2: Review Retiming Results 1.10.3. Step 3: Run Fast Forward Compile 1.10.4. Step 4: Review Fast Forward Results 1.10.5. Step 5: Implement Fast Forward Recommendations 1.10.6. Retiming Restrictions and Workarounds
1.10.2. Step 2: Review Retiming Results x
1.10.2.1. Locate Critical Chains
1.10.3. Step 3: Run Fast Forward Compile x
1.10.3.1. Fast Forward Compile By Hierarchy 1.10.3.2. HyperFlex Settings
1.10.4. Step 4: Review Fast Forward Results x
1.10.4.1. Clock Fmax Summary Report 1.10.4.2. Fast Forward Details Report
1.11. Full Compilation Flow x
1.11.1. Full Compilation Flow with Temporary Optimization Mode
1.13. Exporting Compilation Results x
1.13.1. Exporting a Version-Compatible Compilation Database 1.13.2. Importing a Version-Compatible Compilation Database 1.13.3. Creating a Design Partition 1.13.4. Exporting a Design Partition 1.13.5. Reusing a Design Partition 1.13.6. Viewing Quartus Database File Information 1.13.7. Clearing Compilation Results
1.13.6. Viewing Quartus Database File Information x
1.13.6.1. QDB File Attribute Types
1.14. Integrating Other EDA Tools x
1.14.1. Generating a VQM Netlist for other EDA Tools
1.15. Compiler Optimization Techniques x
1.15.1. Compiler Optimization Modes 1.15.2. Allow Register Retiming 1.15.3. Automatic Gated Clock Conversion 1.15.4. Enable Intermediate Fitter Snapshots 1.15.5. Fast Preserve Option 1.15.6. Fractal Synthesis Optimization
1.15.6. Fractal Synthesis Optimization x
1.15.6.1. Enabling or Disabling Fractal Synthesis
1.16. Synthesis Language Support x
1.16.1. Verilog and SystemVerilog Synthesis Support 1.16.2. VHDL Synthesis Support
1.16.1. Verilog and SystemVerilog Synthesis Support x
1.16.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.16.1.2. Design Libraries 1.16.1.3. Verilog HDL Configuration 1.16.1.4. Initial Constructs and Memory System Tasks 1.16.1.5. Verilog HDL Macros
1.16.1.3. Verilog HDL Configuration x
1.16.1.3.1. Hierarchical Design Configurations
1.16.2. VHDL Synthesis Support x
1.16.2.1. VHDL Input Settings (Settings Dialog Box) 1.16.2.2. VHDL Standard Libraries and Packages 1.16.2.3. VHDL wait Constructs 1.16.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.17. Synthesis Settings Reference x
1.17.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Strategies to Reduce the Overall Compilation Time 2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 2.4. Reducing Placement Time 2.5. Reducing Routing Time 2.6. Reducing Static Timing Analysis Time 2.7. Setting Process Priority 2.8. Reducing Compilation Time Revision History
2.2. Strategies to Reduce the Overall Compilation Time x
2.2.1. Running the ECO Compilation Flow 2.2.2. Enabling Multi-Processor Compilation 2.2.3. Using Block-Based Compilation
2.2.2. Enabling Multi-Processor Compilation x
2.2.2.1. Processor Base Clock Frequency 2.2.2.2. Random Access Memory (RAM) 2.2.2.3. Storage
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
2.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
2.4. Reducing Placement Time x
2.4.1. Placement Effort Multiplier Settings
2.5. Reducing Routing Time x
2.5.1. Identifying Routing Congestion with the Chip Planner
2.5.1. Identifying Routing Congestion with the Chip Planner x
2.5.1.1. Areas with Routing Congestion 2.5.1.2. Congestion due to HDL Coding style
Answers to Top FAQs
1. Design Compilation
2. Reducing Compilation Time
3. Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Quartus® Prime Pro Edition User Guides

1.7.3.7. Example: Using SDC-on-RTL Features

This topic provides some examples of how to use SDC-on-RTL features and set up timing constraints in your design.

You can work with both new and pre-existing designs that incorporate components from diverse sources, including Verilog, VHDL, IPs, and Platform Designer. Suppose your designs contain nodes that require constraint definitions, such as clocks, generated clocks, or asynchronous paths, across various hierarchy levels. In that case, you can efficiently target them using SDC-on-RTL constraints. It is imperative that your chosen design successfully passes the Analysis & Elaboration stages within the compilation flow for seamless and effective testing process.

You can control the number of stages generated during the Analysis & Elaboration using the RTL Analysis Debug Mode option under Project > Settings. This mode is off by default, which means only Elaborated and Swept checkpoints are available, and Instrumented and Constrained checkpoints are unavailable. When you enable this mode, all four checkpoints become available.

Note: Currently, Quartus® Prime IPs use conventional SDCs only, which means if you want to create SDC-on-RTL constraints that interact with IP clocks, define them initially with SDC-on-RTL constraints. These clocks can eventually be overwritten by the IP SDCs. Alternatively, if you do not need the clocks defined at Elaboration, use derive_clocks during Post-Synthesis Static Timing Analysis (STA) to automatically generate clocks temporarily for the Timing Analyzer session.

The following steps demonstrate the process of setting up timing constraints for your designs by targeting RTL node names:

  1. Click New in the left-hand Tasks pane. The New dialog appears.
  2. Click SDC File targeting RTL Names (Read and stored after elaboration).
    Figure 54. New Dialog Box
  3. Click OK.
  4. Within the new SDC-on-RTL file, formulate a comprehensive set of constraints targeting nodes by their RTL names. For information about how to obtain a list of the supported commands, refer to Creating Constraints in SDC-on-RTL SDC Files.
  5. Ensure the constraint targets are correct and the selected design passes the Analysis & Elaboration compilation stage as the constraints are read during this stage and applied to the elaborated netlist. This step is pivotal as it empowers the software to generate a database of your design. Additionally, it grants access to various checkpoints from where you can access the RTL Analyzer.
    Note: The RTL Analyzer assists you in locating specific netlist nodes within your design that require constraint application. It allows you to navigate your design and select your desired target nodes. Subsequently, you can use corresponding Tcl commands generated within the Tcl console to extract hierarchical node names from the Tcl commands. This process streamlines the task of implementing constraints on the netlist nodes. For more information about the RTL Analyzer, refer to Exploring the RTL Analyzer.
    Figure 55. Locating Specific Netlist Nodes in the RTL Analyzer

    Alternatively, you can locate nodes within your target netlist using the Find tool, which is available from the Edit menu in the RTL Analyzer. The Find tool allows you to search objects within the updated database from the checkpoint accessed.

    Figure 56. Find Dialog in the RTL Analyzer

    In addition, you can create your collections by focusing on the inputs and outputs of your design through the use of the get_ports command. Within your design, you can locate specific nets using the get_nets command or target pins using the get_pins command.

    After establishing your timing constraints in your designs, use the following examples as a guide to set up your constraints, specifically focusing on RTL node names, thereby ensuring precision and efficiency throughout your design process.

Targeting Pins of Top-level Instances

In certain scenarios, it is necessary to constrain pins of top-level instances. For example, when defining clocks and reset inputs, you can utilize the get_pins Tcl command followed by the hierarchical pin name to filter each pin as shown in the following: 

get_pins U0|clk_in

This Tcl command returns the input pin clk_in in the instance U0.

Figure 57. Targeting Pins of Top-level Instances
Similarly, you can target other pins of the same instance and apply necessary constraints as shown in the following: 
create_clock -name clk_input -period 10 [get_pins U0|clk_in]
create_generated_clock -name clk_output -source [get_pins U0|clk_in] -divide_by 2 [get_pins U0|clk_out]

Targeting Pins in Cells

When constraining your design, you might need to target cell pins to apply constraints. In such scenarios, you can use the get_pins Tcl command and RTL names to locate specific cell pins, such as clk or d inputs and q outputs. For example: 

get_pins U6|reg_a[0]|clk
get_pins U6|reg_a[0]|d
get_pins U6|reg_a[0]|q
Figure 58. Targeting Pins in Cells Example

These Tcl commands return specific pins of the reg_a[0] register in the U6 instance. You can use the returned collection to constrain paths. For example, from U6|reg_a[0] to U7|regb_a[0][7] as follows: 

set_false_path -from [get_pins U6|reg_a[0]|clk] -to [get_pins U7|regb_a[0][0]|d]

Targeting Pins Using Wildcards

Within your design, you might need to constrain several pins with similar properties and names. In this case, use wildcards to filter the results.

Note: Use the wildcards judiciously and ensure the scope does not include more targets than necessary. Targeting extraneous nodes can limit optimizations and increase compilation runtime and memory.

The get_pins command can target buses porta or portb of U7, as shown in the following: 

get_pins U7|porta[*]
get_pins U7|portb[*]
Figure 59. Targeting Pins Using Wildcards Example

The Tcl command returns a collection of pins from porta[0] to porta[7] and from portb[0] to portb[7]. You can use the returned collection to constrain all objects simultaneously, as shown in the following: 

set_false_path -from [get_pins U5|rega*|clk] -to [get_pins U7|porta[*]]
set_false_path -from [get_pins U6|rega*|clk] -to [get_pins U7|portb[*]]

Example 4. Applying Constraints at Deeper Hierarchies

Within your design, you can apply constraints at different levels of hierarchy using the pipe character (|) to separate hierarchy levels of instances. Constraints are applied when the hierarchy levels match and the string values, including wildcards, match the pin names. For example: 

get_pins U3|U0_lv1|U0_lv2|U0_lv3|flag

The fundamental timing analysis flow requires executing the fitter to elaborate the timing netlist before applying any constraints. In the following example, suppose you intend to constraint a generated clock buried deep within module A:

Figure 60. Applying Constraints at Deeper Hierarchies Example

To achieve this, locate the cell clk_out_mux where the constraint must be applied and identify the pin name COMBOUT. This process often results in a complex path name that can be challenging to decipher, especially when module names are intricate (unlike straightforward names, such as A|B|C). Additionally, suppose the hierarchy evolves in the future. In that case, you must rerun the fitter and delve into the design again to derive the updated path, which can lead to inconsistencies between the design and the constraint targets. You can target the COMBOUT pin as follows: 

get_pins A|B|C|U0|clk_out_mux~0|combout

SDC-on-RTL also offers an efficient means of constraint propagation, enabling you to apply constraints at module boundaries. It ensures that these constraints seamlessly extend to the corresponding leaf instances during the synthesis stage. For instance, revisit the previous example, in which the clock constraint embedded within module A can be established using SDC-on-RTL constraints at the module A's boundaries, specifically focusing on the clk_out pin.

Figure 61. Deeper Design Hierarchies

To target the clk_out pin of module A, use the following filter: 

get_pins A|clk_out

By directing your attention towards pins located at the boundaries of abstract blocks, you gain the flexibility to modify the internal instance hierarchy as needed. Constraints remain effective even if you decide to rename an internal instance within your module, for instance, changing it from A|B|C|U0 to A|X|Y|U0. Importantly, this can be accomplished without requiring alterations to your existing constraints. This demonstrates the robust capabilities of SDC-on-RTL, allowing you to concentrate on boundary pins rather than navigating complex hierarchies. This approach ensures constraint accuracy and simplifies constraint management.

After creating the constraints, rerun the Analysis & Elaboration on the compilation dashboard so that constraints are read and applied to your design. Open the constrained checkpoint of the RTL Analyzer and carefully select the nodes where the constraints were applied. Utilize the Property Viewer to verify the correct application of constraints to these nodes. For additional information, refer to Inspecting SDC-on-RTL Constraints.

Figure 62. Property Viewer in the RTL Analyzer

Utilize the Quartus® Prime software's additional tools to explore and confirm that all SDC constraints were read and successfully applied. Tools like the Constraints viewer launched from the RTL Analyzer can assist you in verifying and cross-probing the constraints with the Schematic Viewer.

Figure 63. Constraints Viewer

Additionally, the reports under Compilation Report > SDC Constraints folder provide a detailed view of the constraints and their locations. Use the Constraint Propagation Report to view how constraints are propagated as the netlist is transformed and inspect where the constraints end up post optimizations.

Important: These tools offer valuable means to verify the accurate application of your constraints. However, if you intend to iterate on the process of defining constraints using the SDC-on-RTL approach, you must rerun the Analysis & Elaboration stage each time. This iterative approach ensures that the constraints are meticulously analyzed during netlist generation, resulting in enhanced performance and seamless integration with your design.
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