Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 4/01/2024
Document Table of Contents

1. Design Compilation

The Quartus® Prime Compiler synthesizes, places, and routes your design before generating device programming files. The Compiler supports a variety of high-level, HDL, and schematic design entry methods. The modules of the Compiler include IP Generation, Analysis & Synthesis, Fitter, Timing Analyzer, and Assembler.
Compilation Dashboard

The Quartus® Prime Pro Edition version of the Compiler supports these advanced features:

  • Supports Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ 7 devices.
  • Incremental Fitter optimization—analyze and optimize after each Fitter stage to maximize performance and shorten total compilation time.
  • Hyper-Aware Design Flow—use Hyper-Retiming and Fast Forward compilation for the highest performance in Stratix® 10 and Agilex™ 7 devices.
  • Partial Reconfiguration—dynamic reconfiguration of a portion of the FPGA, while the remaining FPGA continues to function.
  • Block-Based Design Flows—preservation and reuse of design blocks.