Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 4/01/2024
Document Table of Contents

1.7.5. Viewing Synthesis Reports

The Compilation Report window opens automatically during compilation processing. The Report window displays detailed synthesis results for each partition in the current project revision.
Figure 67.  Synthesis Reports
Table 17.  Synthesis Reports (Design Dependent)
Generated Report Description
Summary Shows summary information about synthesis, such as the status, date, software version, entity name, device family, timing model status, and various types of logic utilization.
Settings Lists the values of all synthesis settings during design processing.
Source Files Read Lists details about all source files in design synthesis. Details include file path, file type, and any library information.
IP Cores Summary Lists details about each IP core instance in design synthesis. Details include IP core name, vendor, version, license type, entity instance, and IP include file.
Partition Summary Shows a summary of partitions in the design. Details include partitions names, hierarchy path, partition type, and partition properties.
Source Assignments A series of reports that list details about source assignments. Details include assignment, value, and source location.
Parameter Settings by Entity Instance A series of reports that list parameter settings for entities in your design. Details in the reports include parameter name, parameter value, and parameter data type.
Note: You can view the parameter settings for a module directly from the Project Navigator by locating the module and selecting View Parameter Settings in its context-sensitive menu. Compilation Report appears, displaying the parameter settings for the entity.
Partition reports Each design partition has a series of reports:
  • Resource Utilization By Entity:

    Lists the quantity of all types of logic usage for each entity in design synthesis.

  • Optimization Results:
    The reports in this folder provide statistics for the following items:
    • Registers, including registers protected by synthesis and registers removed by synthesis
    • Multiplexers, including restructuring that synthesis performs and multiplexers implemented.
  • Post-Synthesis Netlist Statistics
  • Resource Usage Summary:

    Lists the quantity of all types of logic usage for the design partition in design synthesis.

  • RAM Summary:

    Lists RAM usage details for the design partition in design synthesis. Details include the name, type, mode, and density.


Lists all information, warning, and error messages that report conditions observed during the Analysis & Synthesis process.

Warning Messages A series of reports that summarize the warning messages generated during synthesis by providing one entry per message ID, its severity, the count of all its occurrences, and one sample warning message.

A separate report is generated for warnings from each source file. General warning messages that are not associated with a source file are put in a separate report.

Design Assistant (Elaborated) Lists Design Assistant rules that failed during the Analysis & Elaboration stage.
Design Assistant (Synthesized) Lists Design Assistant rules that failed during the Synthesis stage.
SDC Constraints Lists all constraints-related reports. Post-Elaboration Constraints, Post-Synthesis Constraints, and Constraint Propagation Reports are available at the end of synthesis. For more information about these reports, refer to Applying the SDC-on-RTL Constraints.