Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 4/01/2024

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Document Table of Contents

1.14.1. Generating a VQM Netlist for other EDA Tools

The EDA Netlist Writer (quartus_eda) can generate a node-level netlist in Verilog Quartus Mapping File (.vqm) format for use in other EDA tools. You can process the .vqm netlist in other EDA tools to add new modules, partition the netlist, or change connectivity. After third-party tool changes, you resynthesize and compile the .vqm in the Quartus® Prime software.

The .vqm format is standard structural Verilog RTL. The modules can be any Intel FPGA family-specific WYSIWYG type for core logic (such as, flip-flop, LUT, DSP, M20K). EDA Netlist Writer does not support .vqm for periphery modules (such as transceivers, memory interfaces, I/O, or IP including these). The RTL is a fully flattened representation of the entire design hierarchy or partition. The module names capture the original hierarchy, although some renaming can occur to legalize names. There is no truncation of the netlist module names.

To perform .vqm netlist partitioning in other EDA tools, define a design partition that includes only core logic elements. Generate the partition netlist as step 3 describes. After processing the .vqm in third-party tools, resynthesize the .vqm files either independently or as a design partition. If including a black box module instantiation in the .vqm, make connections between existing logic in the .vqm and the black box. Prior to resynthesis, specify the source file (.ip, .v, or .vqm) for the black box in the project .qsf.

VQM Netlist Generation Requirements and Limitations
Requirement or Limitation Description
Design partitions must only include core logic. Design partitions must include only flip-flops, LUTs, DSPs, and on-chip memory. The EDA Netlist Writer does not support .vqm output for periphery modules (such as transceivers, memory interfaces, I/O, or IP that includes these).
Analysis & Synthesis does not support some special characters in instance names that are legal in SystemVerilog. Analysis & Synthesis resolves these characters by placing the standard escape character ‘\’ to escape the special character present in the RTL. If any of the hierarchical constraints (for example, SDC timing constraints) explicitly reference such a special character, modify these characters manually.
Generate .vqm only for a synthesized netlist. The post-fit netlist includes atoms, such as wire-luts, that are not appropriate for resynthesis.
Avoid module or entity name collisions If you add a .vqm, generated from an RTL design file, to the same Quartus® Prime project that generated the .vqm, beware of potential entity or module name collisions. Name collisions can occur if the original RTL file from which the .vqm derives, and the .vqm file itself, both specify the same entity or module name. When the RTL and .vqm files are both present in the project Files list, the Compiler uses the last entry in the list.
Partition assignments might not align with the original design. .vqm generation flattens all logic within a partition unless you specify the –exclude_sub_partitions argument. Compiling a design that has assignments pertaining to a flattened partition causes an error.

To generate a .vqm for processing in other EDA tools, follow these steps:

  1. In the Quartus® Prime software, click Processing > Start > Start Analysis & Synthesis (or run quartus_syn) to synthesize the design netlist.
  2. Create a design partition containing only core logic elements for the .vqm, as Creating a Design Partition describes.
  3. To generate the .vqm in the resynthesis directory, run any of the following commands at the command prompt:
    • To write out the entire design netlist to .vqm:
      quartus_eda –-resynthesis=on <project_name>
    • To write out only a specific design partition netlist to .vqm:
      quartus_eda –-resynthesis=on -partition=<name> <project_name>
    • To write out any sub partition as a black-box netlist to .vqm:
      quartus_eda –-resynthesis=on –exclude_sub_partitions <project_name>
      You can also combine –exclude_sub_partitions with -partition.
  4. View the resulting .vqm in the resynthesis directory, and specify the .vqm as input to your EDA tool.
  5. After processing the .vqm in another EDA tool, add the .vqm as an Quartus® Prime project design file by clicking Project > Add/Remove Files In Project. Avoid module or entity name collisions, as the VQM Netlist Generation Requirements and Limitations table describes.
  6. Run Analysis & Synthesis on the project, followed by the remaining Compiler stages.