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1.1. Compilation Overview
1.2. Using the Compilation Dashboard
1.3. Design Netlist Infrastructure
1.4. Using the Node Finder
1.5. Precompiled Component (PCC) Generation Flow
1.6. Analysis & Elaboration Flow
1.7. Design Synthesis
1.8. Design Place and Route
1.9. Incremental Optimization Flow
1.10. Fast Forward Compilation Flow
1.11. Full Compilation Flow
1.12. Compilation Monitoring Mode
1.13. Exporting Compilation Results
1.14. Integrating Other EDA Tools
1.15. Compiler Optimization Techniques
1.16. Synthesis Language Support
1.17. Synthesis Settings Reference
1.18. Fitter Settings Reference
1.19. Design Compilation Revision History
1.7.3.1. Registering the SDC-on-RTL SDC File
1.7.3.2. Applying the SDC-on-RTL Constraints
1.7.3.3. Inspecting SDC-on-RTL Constraints
1.7.3.4. Creating Constraints in SDC-on-RTL SDC Files
1.7.3.5. Using Entity-Based SDC-on-RTL Constraints
1.7.3.6. Types of SDC Files Used in the Quartus® Prime Software
1.7.3.7. Example: Using SDC-on-RTL Features
1.13.1. Exporting a Version-Compatible Compilation Database
1.13.2. Importing a Version-Compatible Compilation Database
1.13.3. Creating a Design Partition
1.13.4. Exporting a Design Partition
1.13.5. Reusing a Design Partition
1.13.6. Viewing Quartus Database File Information
1.13.7. Clearing Compilation Results
2.1. Factors Affecting Compilation Results
2.2. Strategies to Reduce the Overall Compilation Time
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
2.4. Reducing Placement Time
2.5. Reducing Routing Time
2.6. Reducing Static Timing Analysis Time
2.7. Setting Process Priority
2.8. Reducing Compilation Time Revision History
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2.8. Reducing Compilation Time Revision History
Document Version | Quartus® Prime Version | Changes |
---|---|---|
2023.12.04 | 23.4 |
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2023.06.26 | 23.2 |
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2022.09.26 | 22.3 |
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2022.01.27 | 21.4 |
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2021.11.03 | 21.3 |
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2021.10.04 | 21.3 |
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2021.03.29 | 21.1 |
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2020.09.28 | 20.3 |
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2019.11.11 | 19.3 |
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2019.09.30 | 19.3 |
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2019.07.02 | 19.1 | Added the Using the No-Register Initialization Flow topic. |
2018.10.19 | 18.1 |
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2017.11.06 | 17.1 |
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Date | Version | Changes |
---|---|---|
2017.05.08 | 17.0.0 |
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2016.10.31 | 16.1.0 |
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2016.05.02 | 16.0.0 |
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2015.11.02 | 15.1.0 | Changed instances of Quartus II to Quartus® Prime . |
2014.12.15 | 14.1.0 |
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2014.08.18 |
14.0a10.0 |
Added restriction about smart compilation in Arria 10 devices. |
June 2014 | 14.0.0 | Updated format. |
May 2013 | 13.0.0 | Removed the “Limit to One Fitting Attempt”, “Using Early Timing Estimation”, “Final Placement Optimizations”, and “Using Rapid Recompile” sections. Updated “Placement Effort Multiplier Settings” section. Updated “Identifying Routing Congestion in the Chip Planner” section. General editorial changes throughout the chapter. |
June 2012 | 12.0.0 | Removed survey link. |
November 2011 | 11.0.1 | Template update. |
May 2011 | 11.0.0 |
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December 2010 | 10.1.0 |
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July 2010 | 10.0.0 | Initial release. |