184.108.40.206. Using Simulation Signal Activity Data in Power Analysis
You can specify a Verilog Value Change Dump File (.vcd) generated by simulating a placed and routed gate-level netlist in a supported simulator as the source of signal activity data for power analysis. Third-party simulators can output a .vcd that contains signal activity and static probability information for power analysis. The .vcd includes all routing resources and the logic array resource usage.
To improve the accuracy of power analysis, you can generate a Standard Delay Output (.sdo) file that includes back-annotated delay estimates of the instances of core atoms for ModelSim* simulation. ModelSim* simulation can then output a more accurate .vcd for use as power analysis input. You must run Fitter (Finalize) before generating the .sdo.