188.8.131.52. Using Simulation Signal Activity Data in Power Analysis 184.108.40.206. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 220.127.116.11. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 18.104.22.168. Signal Activities from User Defaults Only
2.5.1. Complete Design Simulation Power Analysis Flow 2.5.2. Modular Design Simulation Power Analysis Flow 2.5.3. Multiple Simulation Power Analysis Flow 2.5.4. Overlapping Simulation Power Analysis Flow 2.5.5. Partial Design Simulation Power Analysis Flow 2.5.6. Vectorless Estimation Power Analysis Flow
3.4.1. Clock Power Management 3.4.2. Pipelining and Retiming 3.4.3. Architectural Optimization 3.4.4. I/O Power Guidelines 3.4.5. Dynamically Controlled On-Chip Terminations (OCT) 3.4.6. Memory Optimization (M20K/MLAB) 3.4.7. DDR Memory Controller Settings 3.4.8. DSP Implementation 3.4.9. Reducing High-Speed Tile (HST) Usage 3.4.10. Unused Transceiver Channels 3.4.11. Periphery Power reduction XCVR Settings
22.214.171.124.1. Generating Signal Activity Data for Power Analysis
To generate and use simulation signal activity data for power analysis:
- To run full compilation on your design, click Processing > Start Compilation.
- To specify settings for simulation output, click Assignments > Settings > EDA Tool Settings > Simulation. Select your simulator in Tool name and the Format for output netlist and Output directory.
Figure 8. EDA Tool Settings for Simulation
- Turn on Map illegal HDL characters. This setting directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL, and results in more accurate data for power analysis.
- Click the Power Analyzer Settings page.
- For Intel® Stratix® 10 designs, to generate a Standard Delay Output (.sdo) file that includes back-annotation of delays for power analysis, refer to Generating Standard Delay Output for Power Analysis.
- Under Input file, turn on Use input files to initialize toggle rates and static probabilities during power analysis.
Figure 9. Specifying Power Analysis Input Files
- To specify a .vcd for power analysis, click Add and specify the File name, Entity, and Simulation period for the .vcd, and click OK.
- To enable glitch filtering during power analysis with the .vcd you generate, turn on Perform glitch filtering on VCD files.
- To run the power analysis, click Start on the Power Analysis step in the Compilation Dashboard. View the toggle rates in the power analysis results.
Note: To improve accuracy of power analysis, the Intel® Quartus® Prime EDA Netlist writer can generate a Standard Delay Output (.sdo) file that includes back-annotation of delays for a design's netlist for use during simulation in ModelSim* . Although the .sdo only contains delay estimates and imprecise timing information, including the .sdo in simulation results in a more accurate output .vcd for power analysis. The EDA Netlist Writer currently supports .sdo file generation only for Verilog .vo simulation in the ModelSim* simulator (not ModelSim* - Intel® FPGA Edition) for Intel® Stratix® 10 designs. The EDA Netlist Writer does not currently support .sdo file generation for any other simulator or device family.
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