Visible to Intel only — GUID: mwh1410384083082
Ixiasoft
Visible to Intel only — GUID: mwh1410384083082
Ixiasoft
2.3.4.1. Clock Node Toggle Rates
For clock nodes, the Power Analyzer uses timing requirements to derive the toggle rate when neither simulation data nor user-entered signal activity data is available. fMAX requirements specify full cycles per second, but each cycle represents a rising transition and a falling transition. For example, a clock fMAX requirement of 100 MHz corresponds to 200 million transitions per second for the clock node.
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