- Updated screenshot in Power Analysis topic.
- Revised description of On-Chip Power Dissipation by Hierarchy report in Viewing Power Analysis Reports topic.
- Removed Write out Power and Thermal Calculator file option description from Settings for Power Analysis topic. This setting is replaced by Power and Thermal Calculator File Name option.
- Revised Running the Power Analyzer topic for Power and Thermal Calculator File Name option.
- Revised Running the Power Analyzer from the Command Line for new GUI option and removal of obsolete commands.
||In the Power Analysis Tools topic, added statements about Intel® Quartus® Prime Power Analyzer accuracy for Intel® Stratix® 10 and Intel® Agilex™ designs.
- In the Settings for Power Analysis topic, modified a Thermal Settings entry in the Power Analyzer and Thermal Settings table. Specifically, changed Apply Recommended Margin to Apply Additional Margin, and modified the description accordingly.
- In the Viewing Power Analysis Reports topic, added the Crypto block type to the On-Chip Power Dissipation by Block Type section.
||Recast the note in the Power Analysis Tools topic for greater clarity.
- In the Power Analysis topic, updated the figure.
- In the Running the Power Analyzer topic, modified step 3 and removed the figure following step 9.
- Changed the title of the Device Operating Condition Settings for Power Analysis topic to Settings for Power Analysis, updated the existing figure and added an additional figure, recast the existing table and added an additional table.
- In the Generating Signal Activity Data for Power Analysis topic, modified step 5 and the figure within step 6.
- In the Viewing Power Analysis Reports topic, made minor changes to the first paragraph of the Thermal Map Visualization section.
- In the Running the Power Analyzer from the Command–Line topic, modified the note at the bottom of the topic.
||Added note to the Specifying the Default Toggle Rate topic.
- Added mention of gate-level simulation to the Specifying Power Analyzer Input, Specifying Signal Activity Data, Using Simulation Signal Activity Data in Power Analysis, and Complete Design Simulation Power Analysis Flow topics,
- Added a sentence to the RTL Simulation Limitation and Avoiding Simulation Node Name Match topics.
- Added a Thermal Map Visualization section to the Viewing Power Analysis Reports topic.
||Added information about the Intel® FPGA Power and Thermal Calculator to the following topics:
- Power Analysis
- Power Analysis Tools
- Running the Power Analyzer from the Command–Line
- Removed references to entity-specific toggle rates in "Specifying Toggle Rates for Specific Nodes." Toggle rates must be either global or node specific.
- Clarified wording of statements about .vcd files in "Simulation Glitch Filtering" topic.
- Corrected typo in "Specifying the Default Toggle Rate" topic.
- Corrected typo in "Running the Power Analyzer from the Command Line" topic.
- Improved explanation in "Generating Standard Delay Output for Power Analysis" topic.
- Corrected broken links to Help.
- Described new support for generation of SDO for use in power analysis.
- Retitled some topic headings for greater clarity.
- Changed the order of some topics for improved flow of information.
- Added descriptions of Power Savings Summary and Parallel Compilation power analysis reports.
- Added new Power Analysis flow diagrams.
- General chapter reorganization.
- Moved Factors Affecting Power Consumption to chapter: Power Optimization.
- Updated figure: Power Analyzer High-level Flow.
- Divided topic: Types of Power Analysis into two topics: Power Estimations and Design Requirements and Design Activity and Power Analysis.
- Updated figure: Power Analysis Tools from Design Concept through Design Implementation and renamed to: Estimation Accuracy for Different Inputs and Power Analysis Tools
- Removed content referring to device families not supported in Intel Quartus Prime Pro Edition.
- In Comparison of the EPE and the Intel Quartus Prime Power Analyzer, updated the data output types that the Power Analyzer supports.
- In Comparison of the EPE and the Intel Quartus Prime Power Analyzer, added row about estimation of transceiver power for features that you enable only through dynamic reconfiguration.
- Specified features not supported by the Power Analyzer.
||Removed references to PowerPlay name. Power analysis occurs in the Intel Quartus Prime Power Analyzer.
- Implemented Intel rebranding.
- Removed support for .vcd generation by the Compiler. Generate .vcd files for power estimation in your EDA simulator.
||Changed instances of Quartus II to Intel Quartus Prime.
- Removed Signal Activities from Full Post-fit Netlist (Timing) Simulation and Signal Activities from Full Post-fit Netlist (Zero Delay) Simulation sections as these are no longer supported.
- Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
||Updated "Current Drawn from Voltage Supplies" to clarify that for SoC devices or for Arria V SoC and Cyclone V SoC devices, there is no standalone ICC_AUX_SHARED current drawn information. The ICC_AUX_SHARED is reported together with ICC_AUX.
- Updated “Types of Power Analyses” on page 8–2, and “Confidence Metric Details” on page 8–23.
- Added “Importance of .vcd” on page 8–20, and “Avoiding Power Estimation and Hardware Measurement Mismatch” on page 8–24
- Updated “Current Drawn from Voltage Supplies” on page 8–22.
- Added “Using the HPS Power Calculator” on page 8–7.
- Template update.
- Minor editorial updates.
- Added links to Quartus II Help, removed redundant material.
- Moved “Creating PowerPlay EPE Spreadsheets” to page 8–6.
- Minor edits.
- Removed references to the Quartus II Simulator.
- Updated Table 8–1 on page 8–6, Table 8–2 on page 8–13, and Table 8–3 on page 8–14.
- Updated Figure 8–3 on page 8–9, Figure 8–4 on page 8–10, and Figure 8–5 on page 8–12.
- Updated “Creating PowerPlay EPE Spreadsheets” on page 8–6 and “Simulation Results” on page 8–10.
- Added “Signal Activities from Full Post-fit Netlist (Zero Delay) Simulation” on page 8–19 and “Generating a .vcd from Full Post-fit Netlist (Zero Delay) Simulation” on page 8–21.
- Minor changes to “Generating a .vcd from ModelSim Software” on page 8–21.
- Updated Figure 11–8 on page 11–24.
- This chapter was chapter 11 in version 8.1.
- Removed Figures 11-10, 11-11, 11-13, 11-14, and 11-17 from 8.1 version.
- Updated for the Quartus II software version 8.1.
- Replaced Figure 11-3.
- Replaced Figure 11-14.
- Updated Figure 11–5.
- Updated “Types of Power Analyses” on page 11–5.
- Updated “Operating Conditions” on page 11–9.
- Updated “PowerPlay Power Analyzer Compilation Report” on page 11–31.
- Updated “Current Drawn from Voltage Supplies” on page 11–32.