188.8.131.52. Using Simulation Signal Activity Data in Power Analysis 184.108.40.206. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 220.127.116.11. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 18.104.22.168. Signal Activities from User Defaults Only
2.5.1. Complete Design Simulation Power Analysis Flow 2.5.2. Modular Design Simulation Power Analysis Flow 2.5.3. Multiple Simulation Power Analysis Flow 2.5.4. Overlapping Simulation Power Analysis Flow 2.5.5. Partial Design Simulation Power Analysis Flow 2.5.6. Vectorless Estimation Power Analysis Flow
3.4.1. Clock Power Management 3.4.2. Pipelining and Retiming 3.4.3. Architectural Optimization 3.4.4. I/O Power Guidelines 3.4.5. Dynamically Controlled On-Chip Terminations (OCT) 3.4.6. Memory Optimization (M20K/MLAB) 3.4.7. DDR Memory Controller Settings 3.4.8. DSP Implementation 3.4.9. Reducing High-Speed Tile (HST) Usage 3.4.10. Unused Transceiver Channels 3.4.11. Periphery Power reduction XCVR Settings
22.214.171.124.2. Generating Standard Delay Output for Power Analysis
To improve accuracy of power analysis, you can generate a Standard Delay Output (.sdo) file that includes back-annotated delay estimates for ModelSim* simulation. ModelSim* simulation can then output a more accurate .vcd for use as power analysis input. You must run Fitter (Finalize) before generating the .sdo.
Using an SDO in Power Analysis
- Click Assignments > Settings > EDA Tool Settings > Simulation. In Tool name select ModelSim* and Verilog for Format for output netlist.
Figure 10. More EDA Netlist Writer Settings
- Click More EDA Netlist Writer Settings. Set Enable SDO Generation for Power Estimation to On. Set Generate Power Estimate Scripts to ALL_NODES.
- To run the Fitter, click Processing > Start > Start Fitter (Finalize).
- Create a representative testbench (.vt) that exercises the design functions appropriately.
- To specify the appropriate hierarchy level for signals in the output .vcd, add the following line to the project .qsf file: 1
set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME <DUT instance path> -section_id eda_simulation
- After Fitter processing is complete, click Processing > Start > Start EDA Netlist Writer. EDA Netlist Writer generates the following files in /<project>/simulation/modelsim/power/:
- <project>.vo (contains a reference to the .sdo file by default)
- <project>_dump_all_vcd_nodes.tcl—specifies nodes to save in .vcd
- <project>_v.sdo—back-annotated delay estimates
- Create a ModelSim* script (.do) to load the design and testbench, start ModelSim* , and then source the .do script.
- To specify the signals ModelSim* includes in the .vcd file, source *_dump_all_vcd_nodes.tcl in ModelSim* .
- To generate the .vcd file, simulate the test bench and netlist in ModelSim* . The .vcd file generates according to your specifications.
- Specify the .vcd as an input to power analysis, as Generating Signal Activity Data for Power Analysis describes.
Note: The EDA Netlist Writer currently supports .sdo file generation only for Verilog .vo simulation in the ModelSim* simulator (not ModelSim* - Intel® FPGA Edition) for Intel® Stratix® 10 designs. The EDA Netlist Writer does not currently support .sdo file generation for any other simulator or device family.
1 Specify the full hierarchical path in the testbench, not just the instance name. For example, specify a|b|c, not just c.
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