220.127.116.11. Using Simulation Signal Activity Data in Power Analysis 18.104.22.168. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 22.214.171.124. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 126.96.36.199. Signal Activities from User Defaults Only
2.5.1. Complete Design Simulation Power Analysis Flow 2.5.2. Modular Design Simulation Power Analysis Flow 2.5.3. Multiple Simulation Power Analysis Flow 2.5.4. Overlapping Simulation Power Analysis Flow 2.5.5. Partial Design Simulation Power Analysis Flow 2.5.6. Vectorless Estimation Power Analysis Flow
3.4.1. Clock Power Management 3.4.2. Pipelining and Retiming 3.4.3. Architectural Optimization 3.4.4. I/O Power Guidelines 3.4.5. Dynamically Controlled On-Chip Terminations (OCT) 3.4.6. Memory Optimization (M20K/MLAB) 3.4.7. DDR Memory Controller Settings 3.4.8. DSP Implementation 3.4.9. Reducing High-Speed Tile (HST) Usage 3.4.10. Unused Transceiver Channels 3.4.11. Periphery Power reduction XCVR Settings
2.5.4. Overlapping Simulation Power Analysis Flow
You can perform a simulation on the entire design, and more exhaustive simulations on a submodule, such as 8b10b_rxerr. The following table lists the import specification for overlapping simulations:
In this case, the software uses signal activities from error_cases.vcd for all the nodes in the generated .vcd and uses signal activities from full_design.vcd for only those nodes that do not overlap with nodes in error_cases.vcd. In general, the more specific hierarchy (the most bottom-level module) derives signal activities for overlapping nodes.
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