Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 12/12/2022

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Document Table of Contents Merge Clocks

Evaluate the possibility of merging clocks and PLLs in the design.

Design 2clks & 2PLLs 1 Clk & 1 PLL


6.079W 5.46W
  • 2clks & 2PLLs

    Clk1:350Mhz, Fanout 46788

    Clk2: 365Mhz, Fanout 2450

  • 1Clk & 1PLL

    Merge clks

    clk: 365Mhz, Fanout 51277