126.96.36.199. Using Simulation Signal Activity Data in Power Analysis 188.8.131.52. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 184.108.40.206. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 220.127.116.11. Signal Activities from User Defaults Only
2.5.1. Complete Design Simulation Power Analysis Flow 2.5.2. Modular Design Simulation Power Analysis Flow 2.5.3. Multiple Simulation Power Analysis Flow 2.5.4. Overlapping Simulation Power Analysis Flow 2.5.5. Partial Design Simulation Power Analysis Flow 2.5.6. Vectorless Estimation Power Analysis Flow
3.4.1. Clock Power Management 3.4.2. Pipelining and Retiming 3.4.3. Architectural Optimization 3.4.4. I/O Power Guidelines 3.4.5. Dynamically Controlled On-Chip Terminations (OCT) 3.4.6. Memory Optimization (M20K/MLAB) 3.4.7. DDR Memory Controller Settings 3.4.8. DSP Implementation 3.4.9. Reducing High-Speed Tile (HST) Usage 3.4.10. Unused Transceiver Channels 3.4.11. Periphery Power reduction XCVR Settings
3.4.1. Clock Power Management
Clocks represent a significant portion of dynamic power consumption due to their high switching activity and long paths. Actual clock-related power consumption is higher, because the power consumption of a block includes local clock distribution within logic, memory, and DSP or multiplier blocks.
The Intel® Quartus® Prime software optimizes clock routing power automatically, enabling only those portions of the clock network that are necessary to feed downstream registers.
Did you find the information on this page useful?