126.96.36.199. Using Simulation Signal Activity Data in Power Analysis 188.8.131.52. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 184.108.40.206. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 220.127.116.11. Signal Activities from User Defaults Only
2.5.1. Complete Design Simulation Power Analysis Flow 2.5.2. Modular Design Simulation Power Analysis Flow 2.5.3. Multiple Simulation Power Analysis Flow 2.5.4. Overlapping Simulation Power Analysis Flow 2.5.5. Partial Design Simulation Power Analysis Flow 2.5.6. Vectorless Estimation Power Analysis Flow
3.4.1. Clock Power Management 3.4.2. Pipelining and Retiming 3.4.3. Architectural Optimization 3.4.4. I/O Power Guidelines 3.4.5. Dynamically Controlled On-Chip Terminations (OCT) 3.4.6. Memory Optimization (M20K/MLAB) 3.4.7. DDR Memory Controller Settings 3.4.8. DSP Implementation 3.4.9. Reducing High-Speed Tile (HST) Usage 3.4.10. Unused Transceiver Channels 3.4.11. Periphery Power reduction XCVR Settings
2.1. Power Analysis Tools
The Intel® Quartus® Prime Design Suite provides tools to analyze the power consumption of your FPGA design at different stages of the design process.
- Intel® FPGA Power and Thermal Calculator (PTC)—estimates power supply and system thermal requirements before compiling the design, or anytime during the design phase. Supports Intel® Stratix® 10 and Intel® Agilex™ devices.
- Intel® Quartus® Prime Power Analyzer (QPA)—estimates power consumption for a post-fit design, allowing you establish guidelines for the power budget.
- Early Power Estimator (EPE) spreadsheet—estimates power consumption for power supply planning before compiling the design. Supports Intel® Arria® 10 and Intel® Stratix® 10 devices. (For versions of the Intel® Quartus® Prime software later than version 19.4, Intel® Stratix® 10 devices are supported in the Intel® FPGA Power and Thermal Calculator.)
Figure 1. Estimation Accuracy for Different Inputs and Power Analysis Tools
The accuracy of the power model is determined on a per-power-rail basis for the Intel® Quartus® Prime Power Analyzer.
- For most Intel® Stratix® 10 designs, the Intel® Quartus® Prime Power Analyzer has the following accuracy, assuming final power models: Within 10% of silicon for the majority of power rails with higher power, assuming accurate inputs and toggle rates.
- For most Intel® Agilex™ designs, the Intel® Quartus® Prime Power Analyzer has the following accuracy, assuming final power models: Within 10% of silicon for all power rails, assuming accurate inputs and toggle rates.
|Characteristic||EPE / PTC||Intel® Quartus® Prime Power Analyzer|
|When to use||Any time
Note: For post-fit power analysis, you get better results with the Intel® Quartus® Prime Power Analyzer.
EPE: Spreadsheet program.
Intel® FPGA PTC: Integrated into the Intel® Quartus® Prime software, and is also available as a standalone tool.
|The Intel® Quartus® Prime software|
|Accuracy||Medium||Medium to very high|
Note: The EPE and Power Analyzer outputs vary by device family.
|Estimation of transceiver power for dynamic reconfiguration features||Includes an estimation of the incremental power consumption by these features.||Not included|
The Intel® Quartus® Prime Power Analyzer does not support power analysis of the following Intel® FPGA IP:
- Intel® Stratix® 10 HBM2 IP
- Intel® Stratix® 10 HPS IP
- Intel® Arria® 10 HPS IP
For power estimation of Intel® Arria® 10 HPS IP, and for power estimation in the Intel® Quartus® Prime software version 19.4 or earlier, you can obtain power estimations using the Early Power Estimator spreadsheet (EPE).
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