Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

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ID 683174
Date 12/12/2022
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Power Analysis 3. Power Optimization 4. Power Analysis and Optimization Document Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Power Analysis x
2.1. Power Analysis Tools 2.2. Running the Power Analyzer 2.3. Specifying Power Analyzer Input 2.4. Viewing Power Analysis Reports 2.5. Power Analysis in Modular Design Flows 2.6. Scripting Support 2.7. Power Analysis Revision History
2.3. Specifying Power Analyzer Input x
2.3.1. Settings for Power Analysis 2.3.2. Specifying Signal Activity Data 2.3.3. Specifying the Default Toggle Rate 2.3.4. Specifying Toggle Rates for Specific Nodes 2.3.5. Avoiding Simulation Node Name Match
2.3.2. Specifying Signal Activity Data x
2.3.2.1. Using Simulation Signal Activity Data in Power Analysis 2.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 2.3.2.3. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 2.3.2.4. Signal Activities from User Defaults Only
2.3.2.1. Using Simulation Signal Activity Data in Power Analysis x
2.3.2.1.1. Generating Signal Activity Data for Power Analysis 2.3.2.1.2. Generating Standard Delay Output for Power Analysis 2.3.2.1.3. Simulation Glitch Filtering
2.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation x
2.3.2.2.1. RTL Simulation Limitation
2.3.4. Specifying Toggle Rates for Specific Nodes x
2.3.4.1. Clock Node Toggle Rates
2.5. Power Analysis in Modular Design Flows x
2.5.1. Complete Design Simulation Power Analysis Flow 2.5.2. Modular Design Simulation Power Analysis Flow 2.5.3. Multiple Simulation Power Analysis Flow 2.5.4. Overlapping Simulation Power Analysis Flow 2.5.5. Partial Design Simulation Power Analysis Flow 2.5.6. Vectorless Estimation Power Analysis Flow
2.5.5. Partial Design Simulation Power Analysis Flow x
2.5.5.1. Specifying Start and End Time for Signal Activity Calculations
2.6. Scripting Support x
2.6.1. Running the Power Analyzer from the Command–Line
3. Power Optimization x
3.1. Factors Affecting Power Consumption 3.2. Design Space Explorer II for Power-Driven Optimization 3.3. Power-Driven Compilation 3.4. Design Guidelines 3.5. Power Optimization Advisor 3.6. Power Optimization Revision History
3.1. Factors Affecting Power Consumption x
3.1.1. Design Activity and Power Analysis 3.1.2. Device Selection 3.1.3. Environmental Conditions 3.1.4. Device Resource Usage 3.1.5. Signal Activity
3.1.4. Device Resource Usage x
3.1.4.1. Number, Type, and Loading of I/O Pins 3.1.4.2. Number and Type of Hard Logic Blocks 3.1.4.3. Number and Type of Global Signals
3.1.5. Signal Activity x
3.1.5.1. Toggle Rate 3.1.5.2. Static Probability
3.3. Power-Driven Compilation x
3.3.1. Power-Driven Synthesis 3.3.2. Power-Driven Fitter 3.3.3. Area-Driven Synthesis 3.3.4. Gate-Level Register Retiming 3.3.5. Intel® Quartus® Prime Compiler Settings 3.3.6. Assignment Editor Options
3.3.1. Power-Driven Synthesis x
3.3.1.1. Memory Block Optimization 3.3.1.2. Power-Aware Logic Mapping 3.3.1.3. Power-Aware Memory Balancing
3.4. Design Guidelines x
3.4.1. Clock Power Management 3.4.2. Pipelining and Retiming 3.4.3. Architectural Optimization 3.4.4. I/O Power Guidelines 3.4.5. Dynamically Controlled On-Chip Terminations (OCT) 3.4.6. Memory Optimization (M20K/MLAB) 3.4.7. DDR Memory Controller Settings 3.4.8. DSP Implementation 3.4.9. Reducing High-Speed Tile (HST) Usage 3.4.10. Unused Transceiver Channels 3.4.11. Periphery Power reduction XCVR Settings
3.4.1. Clock Power Management x
3.4.1.1. Clock Gating 3.4.1.2. Clock Enable in Memory Blocks 3.4.1.3. LAB Clock Power 3.4.1.4. Clock Enables 3.4.1.5. Global Signals 3.4.1.6. Merge Clocks
3.4.1.1. Clock Gating x
3.4.1.1.1. Root Clock Gate 3.4.1.1.2. Sector Clock Gate 3.4.1.1.3. I/O PLL Clock Gate
3.4.1.3. LAB Clock Power x
3.4.1.3.1. LAB-Wide Clock Enable Example
3.4.1.5. Global Signals x
3.4.1.5.1. Viewing Clock Details in the Chip Planner
3.4.6. Memory Optimization (M20K/MLAB) x
3.4.6.1. Implementation 3.4.6.2. Rd/Wr Enables
3.4.11. Periphery Power reduction XCVR Settings x
3.4.11.1. Transceiver Settings 3.4.11.2. I/O Current Strength
3.5. Power Optimization Advisor x
3.5.1. Set Realistic Timing Constraints 3.5.2. Appropriate Device Family 3.5.3. Dynamic Power 3.5.4. Static Power 3.5.5. Appropriate I/O Standards 3.5.6. Use RAM Blocks 3.5.7. Shut Down RAM Blocks 3.5.8. Clock Enables on Logic 3.5.9. Pipeline Logic to Reduce Glitching
3.5.1. Set Realistic Timing Constraints x
3.5.1.1. Find Timing Information
1. Answers to Top FAQs
2. Power Analysis
3. Power Optimization
4. Power Analysis and Optimization Document Archive
A. Intel® Quartus® Prime Pro Edition User Guides

2.1. Power Analysis Tools

The Intel® Quartus® Prime Design Suite provides tools to analyze the power consumption of your FPGA design at different stages of the design process.

  • Intel® FPGA Power and Thermal Calculator (PTC)—estimates power supply and system thermal requirements before compiling the design, or anytime during the design phase. Supports Intel® Stratix® 10 and Intel® Agilex™ devices.
  • Intel® Quartus® Prime Power Analyzer (QPA)—estimates power consumption for a post-fit design, allowing you establish guidelines for the power budget.
  • Early Power Estimator (EPE) spreadsheet—estimates power consumption for power supply planning before compiling the design. Supports Intel® Arria® 10 and Intel® Stratix® 10 devices. (For versions of the Intel® Quartus® Prime software later than version 19.4, Intel® Stratix® 10 devices are supported in the Intel® FPGA Power and Thermal Calculator.)
Figure 1. Estimation Accuracy for Different Inputs and Power Analysis Tools


The accuracy of the power model is determined on a per-power-rail basis for the Intel® Quartus® Prime Power Analyzer.
  • For most Intel® Stratix® 10 designs, the Intel® Quartus® Prime Power Analyzer has the following accuracy, assuming final power models: Within 10% of silicon for the majority of power rails with higher power, assuming accurate inputs and toggle rates.
  • For most Intel® Agilex™ designs, the Intel® Quartus® Prime Power Analyzer has the following accuracy, assuming final power models: Within 10% of silicon for all power rails, assuming accurate inputs and toggle rates.
Table 1.  Comparison of EPE/ Intel® FPGA PTC and Intel® Quartus® Prime Power Analyzer Capabilities
Characteristic EPE / PTC Intel® Quartus® Prime Power Analyzer
When to use Any time
Note: For post-fit power analysis, you get better results with the Intel® Quartus® Prime Power Analyzer.
Post-fit
Software requirements

EPE: Spreadsheet program.

Intel® FPGA PTC: Integrated into the Intel® Quartus® Prime software, and is also available as a standalone tool.

The Intel® Quartus® Prime software
Accuracy Medium Medium to very high
Data inputs
  • Resource usage estimates
  • Clock requirements
  • Environmental conditions
  • Toggle rate
  • Post-fit design
  • Clock requirements
  • Signal activity defaults
  • Environmental conditions
  • Register transfer level (RTL) simulation results (optional)
  • Post-fit simulation results (optional)
  • Signal activities per node or entity (optional)
Data outputs
Note: The EPE and Power Analyzer outputs vary by device family.
  • Total thermal power dissipation
  • Thermal static power
  • Thermal dynamic power
  • Off-chip power dissipation
  • Current drawn from voltage supplies
  • Total thermal power
  • Thermal static power
  • Thermal dynamic power
  • Thermal I/O power
  • Thermal power by design hierarchy
  • Thermal power by block type
  • Thermal power dissipation by clock domain
  • Device supply currents
Estimation of transceiver power for dynamic reconfiguration features Includes an estimation of the incremental power consumption by these features. Not included
Note:
The Intel® Quartus® Prime Power Analyzer does not support power analysis of the following Intel® FPGA IP:
  • Intel® Stratix® 10 HBM2 IP
  • Intel® Stratix® 10 HPS IP
  • Intel® Arria® 10 HPS IP
In versions of the Intel® Quartus® Prime software later than 19.4, you can obtain power estimations for the Intel® Stratix® 10 HBM2 IP and Intel® Stratix® 10 HPS IP using the Intel® FPGA Power and Thermal Calculator (PTC).

For power estimation of Intel® Arria® 10 HPS IP, and for power estimation in the Intel® Quartus® Prime software version 19.4 or earlier, you can obtain power estimations using the Early Power Estimator spreadsheet (EPE).

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