Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

ID 683174
Date 12/12/2022
Public

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3.4.1.3.1. LAB-Wide Clock Enable Example

This VHDL code makes use of a LAB-wide clock enable. This clock-gating logic is automatically turned into an LAB-level clock enable signal.
IF clk'event AND clock = '1' THEN
     IF logic_is_enabled = '1' THEN
       reg <= value;
     ELSE
       reg <= reg;
     END IF;
END IF;