Avalon® Interface Specifications

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ID 683091
Date 9/26/2022
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
1. Introduction to the Avalon® Interface Specifications x
1.1. Avalon® Properties and Parameters 1.2. Signal Roles 1.3. Interface Timing 1.4. Example: Avalon® Interfaces in System Designs
2. Avalon® Clock and Reset Interfaces x
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
3. Avalon® Memory-Mapped Interfaces x
3.1. Introduction to Avalon® Memory-Mapped Interfaces 3.2. Avalon® Memory Mapped Interface Signal Roles 3.3. Interface Properties 3.4. Timing 3.5. Transfers 3.6. Address Alignment 3.7. Avalon® -MM Agent Addressing
3.5. Transfers x
3.5.1. Typical Read and Write Transfers 3.5.2. Transfers Using the waitrequestAllowance Property 3.5.3. Read and Write Transfers with Fixed Wait-States 3.5.4. Pipelined Transfers 3.5.5. Burst Transfers 3.5.6. Read and Write Responses
3.5.2. Transfers Using the waitrequestAllowance Property x
3.5.2.1. waitrequestAllowance Equals Two 3.5.2.2. waitrequestAllowance Equals One 3.5.2.3. waitrequestAllowance Equals Two - Not Recommended 3.5.2.4. waitrequestAllowance Compatibility for Avalon® -MM Host and Agent Interfaces 3.5.2.5. waitrequestAllowance Error Conditions
3.5.4. Pipelined Transfers x
3.5.4.1. Pipelined Read Transfer with Variable Latency 3.5.4.2. Pipelined Read Transfers with Fixed Latency
3.5.5. Burst Transfers x
3.5.5.1. Write Bursts 3.5.5.2. Read Bursts 3.5.5.3. Line–Wrapped Bursts
3.5.6. Read and Write Responses x
3.5.6.1. Transaction Order for Avalon® -MM Read and Write Responses (Hosts and Agents) 3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram
3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram x
3.5.6.2.1. minimumResponseLatency Timing Diagram with readdatavalid or writeresponsevalid
4. Avalon® Interrupt Interfaces x
4.1. Interrupt Sender 4.2. Interrupt Receiver
4.1. Interrupt Sender x
4.1.1. Avalon® Interrupt Sender Signal Roles 4.1.2. Interrupt Sender Properties
4.2. Interrupt Receiver x
4.2.1. Avalon® Interrupt Receiver Signal Roles 4.2.2. Interrupt Receiver Properties 4.2.3. Interrupt Timing
5. Avalon® Streaming Interfaces x
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
5.3. Signal Sequencing and Timing x
5.3.1. Synchronous Interface 5.3.2. Clock Enables
5.9. Data Transfer with Backpressure x
5.9.1. Data Transfers Using readyLatency and readyAllowance 5.9.2. Data Transfers Using readyLatency
6. Avalon® Streaming Credit Interfaces x
6.1. Terms and Concepts 6.2. Avalon® Streaming Credit Interface Signal Roles 6.3. Avalon® Streaming Credit User Signals
6.2. Avalon® Streaming Credit Interface Signal Roles x
6.2.1. Synchronous Interface 6.2.2. Typical Data Transfers 6.2.3. Returning the Credits
6.3. Avalon® Streaming Credit User Signals x
6.3.1. Per-Symbol User Signal 6.3.2. Per-Packet User Signal
7. Avalon® Conduit Interfaces x
7.1. Avalon® Conduit Signal Roles 7.2. Conduit Properties
8. Avalon® Tristate Conduit Interface x
8.1. Avalon® Tristate Conduit Signal Roles 8.2. Tristate Conduit Properties 8.3. Tristate Conduit Timing
1. Introduction to the Avalon® Interface Specifications
2. Avalon® Clock and Reset Interfaces
3. Avalon® Memory-Mapped Interfaces
4. Avalon® Interrupt Interfaces
5. Avalon® Streaming Interfaces
6. Avalon® Streaming Credit Interfaces
7. Avalon® Conduit Interfaces
8. Avalon® Tristate Conduit Interface
A. Deprecated Signals
B. Document Revision History for the Avalon® Interface Specifications

3.5.5.1. Write Bursts

These rules apply when a write burst begins with burstcount greater than one:

  • When a burstcount of <n> is presented at the beginning of the burst, the agent must accept <n> successive units of writedata to complete the burst. Arbitration between the host-agent pair remains locked until the burst completes. This lock guarantees that no other host can execute transactions on the agent until the write burst completes.
  • The agent must only capture writedata when write asserts. During the burst, the host can deassert write indicating that writedata is invalid. Deasserting write does not terminate the burst. The write deassertion delays the burst and no other host can access the agent, reducing the transfer efficiency.
  • The agent delays a transfer by asserting waitrequest forcing writedata, write, burstcount, and byteenable to be held constant.
  • The functionality of the byteenable signal is the same for bursting and non-bursting agents. For a 32-bit host burst-writing to a 64-bit agent, starting at byte address 4, the first write transfer seen by the agent is at its address 0, with byteenable = 8'b11110000. The byteenables can change for different words of the burst.
  • The byteenable signals do not all have to be asserted. A burst host writing partial words can use the byteenable signal to identify the data being written.
  • Writes with byteenable signals being all 0's are simply passed on to the Avalon® -MM agent as valid transactions.
  • The constantBurstBehavior property specifies the behavior of the burst signals.
    • When constantBurstBehavior is true for a host, the host holds address and burstcount stable throughout a burst. When true for a agent, constantBurstBehavior declares that the agent expects address and burstcount to be held stable throughout a burst.
    • When constantBurstBehavior is false, the host holds address and burstcount stable only for the first transaction of a burst. When constantBurstBehavior is false, the agent samples address and burstcount only on the first transaction of a burst.
Figure 14. Write Burst with constantBurstBehavior Set to False for Host and AgentThe following figure demonstrates a agent write burst of length 4. In this example, the agent asserts waitrequest twice delaying the burst.

The numbers in this timing diagram mark the following transitions:

  1. The host asserts address, burstcount, write, and drives the first unit of writedata.
  2. The agent immediately asserts waitrequest, indicating that the agent is not ready to proceed with the transfer.
  3. waitrequest is low. The agent captures addr1, burstcount, and the first unit of writedata. On subsequent cycles of the transfer, address and burstcount are ignored.
  4. The agent captures the second unit of data at the rising edge of clk.
  5. The burst is paused while write is deasserted.
  6. The agent captures the third unit of data at the rising edge of clk.
  7. The agent asserts waitrequest. In response, all outputs are held constant through another clock cycle.
  8. The agent captures the last unit of data on this rising edge of clk. The agent write burst ends.

In the figure above, the beginbursttransfer signal is asserted for the first clock cycle of a burst and is deasserted on the next clock cycle. Even if the agent asserts waitrequest, the beginbursttransfer signal is only asserted for the first clock cycle.

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