1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
188.8.131.52. Write Bursts
These rules apply when a write burst begins with burstcount greater than one:
- When a burstcount of <n> is presented at the beginning of the burst, the agent must accept <n> successive units of writedata to complete the burst. Arbitration between the host-agent pair remains locked until the burst completes. This lock guarantees that no other host can execute transactions on the agent until the write burst completes.
- The agent must only capture writedata when write asserts. During the burst, the host can deassert write indicating that writedata is invalid. Deasserting write does not terminate the burst. The write deassertion delays the burst and no other host can access the agent, reducing the transfer efficiency.
- The agent delays a transfer by asserting waitrequest forcing writedata, write, burstcount, and byteenable to be held constant.
- The functionality of the byteenable signal is the same for bursting and non-bursting agents. For a 32-bit host burst-writing to a 64-bit agent, starting at byte address 4, the first write transfer seen by the agent is at its address 0, with byteenable = 8'b11110000. The byteenables can change for different words of the burst.
- The byteenable signals do not all have to be asserted. A burst host writing partial words can use the byteenable signal to identify the data being written.
- Writes with byteenable signals being all 0's are simply passed on to the Avalon® -MM agent as valid transactions.
- The constantBurstBehavior property specifies the behavior of the burst signals.
- When constantBurstBehavior is true for a host, the host holds address and burstcount stable throughout a burst. When true for a agent, constantBurstBehavior declares that the agent expects address and burstcount to be held stable throughout a burst.
- When constantBurstBehavior is false, the host holds address and burstcount stable only for the first transaction of a burst. When constantBurstBehavior is false, the agent samples address and burstcount only on the first transaction of a burst.
Figure 14. Write Burst with constantBurstBehavior Set to False for Host and AgentThe following figure demonstrates a agent write burst of length 4. In this example, the agent asserts waitrequest twice delaying the burst.
The numbers in this timing diagram mark the following transitions:
- The host asserts address, burstcount, write, and drives the first unit of writedata.
- The agent immediately asserts waitrequest, indicating that the agent is not ready to proceed with the transfer.
- waitrequest is low. The agent captures addr1, burstcount, and the first unit of writedata. On subsequent cycles of the transfer, address and burstcount are ignored.
- The agent captures the second unit of data at the rising edge of clk.
- The burst is paused while write is deasserted.
- The agent captures the third unit of data at the rising edge of clk.
- The agent asserts waitrequest. In response, all outputs are held constant through another clock cycle.
- The agent captures the last unit of data on this rising edge of clk. The agent write burst ends.
In the figure above, the beginbursttransfer signal is asserted for the first clock cycle of a burst and is deasserted on the next clock cycle. Even if the agent asserts waitrequest, the beginbursttransfer signal is only asserted for the first clock cycle.
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