Avalon® Interface Specifications

ID 683091
Date 9/26/2022
Document Table of Contents

5.9. Data Transfer with Backpressure

The sink asserts ready for a single clock cycle to indicate it is ready for an active cycle. If the sink is ready for data, the cycle is a ready cycle. During a ready cycle, the source may assert valid and provide data to the sink. If the source has no data to send, the source deasserts valid and can drive data to any value.

Interfaces that support backpressure define the readyLatency parameter to indicate the number of cycles from the time that ready is asserted until valid data can be driven. If the readyLatency is nonzero, cycle <n + readyLatency> is a ready cycle if ready is asserted on cycle <n>.

When readyLatency = 0, data transfer only happens when ready and valid are asserted on the same cycle. In this mode, the source does not receive the sink’s ready signal before sending valid data. The source provides the data and asserts valid whenever the source has valid data. The source waits for the sink to capture the data and assert ready. The source can change the data at any time. The sink only captures input data from the source when ready and valid are both asserted.

When readyLatency >= 1, the sink asserts ready before the ready cycle itself. The source can respond during the appropriate subsequent cycle by asserting valid. The source may not assert valid during cycles that are not ready cycles.

readyAllowance defines the number of transfers that the sink can capture when ready is deasserted. When readyAllowance = 0, the sink cannot accept any transfers after ready is deasserted. If readyAllowance = <n> where n > 0, the sink can accept up to <n> transfers after ready is deasserted.