Visible to Intel only — GUID: nik1412467922642
Ixiasoft
Visible to Intel only — GUID: nik1412467922642
Ixiasoft
1.3. Interface Timing
Most Avalon® interfaces must not be edge sensitive to signals other than the clock and reset. Other signals may transition multiple times before they stabilize. The exact timing of signals between clock edges varies depending upon the characteristics of the selected Intel® FPGA. This specification does not specify electrical characteristics. Refer to the appropriate device documentation for electrical specifications.
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