Avalon® Interface Specifications

ID 683091
Date 9/26/2022
Public
Document Table of Contents
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1.3. Interface Timing

Subsequent chapters of this document include timing information that describes transfers for individual interface types. There is no guaranteed performance for any of these interfaces. Actual performance depends on many factors, including component design and system implementation.

Most Avalon® interfaces must not be edge sensitive to signals other than the clock and reset. Other signals may transition multiple times before they stabilize. The exact timing of signals between clock edges varies depending upon the characteristics of the selected Intel® FPGA. This specification does not specify electrical characteristics. Refer to the appropriate device documentation for electrical specifications.