Avalon® Interface Specifications

ID 683091
Date 9/26/2022
Document Table of Contents

2.6. Reset Sink

Table 5.  Reset Input Signal RolesThe reset_req signal is an optional signal that you can use to prevent memory content corruption by performing reset handshake prior to an asynchronous reset assertion.
Signal Role Width Direction Required Description
reset, reset_n 1 Input Yes Resets the internal logic of an interface or component to a user-defined state. The synchronous properties of the reset are defined by the synchronousEdges parameter.
reset_req 1 input No Early indication of reset signal. This signal acts as a least a one-cycle warning of pending reset for ROM primitives. Use reset_req to disable the clock enable or mask the address bus of an on-chip memory, to prevent the address from transitioning when an asynchronous reset input is asserted.