Avalon® Interface Specifications

ID 683091
Date 9/26/2022
Document Table of Contents

4.2.3. Interrupt Timing

The Avalon® -MM host services the priority 0 interrupt before the priority 1 interrupt.
Figure 19. Interrupt TimingIn the following figure, interrupt 0 has higher priority. The interrupt receiver is in the process of handling int1 when int0 is asserted. The int0 handler is called and completes. Then, the int1 handler resumes. The diagram shows int0 deasserts at time 1. int1 deasserts at time 2.